A Power-Efficient Continuous-Time Incremental Sigma-Delta ADC for Neural Recording Systems
2015 (English)In: IEEE Transactions on Circuits and Systems Part 1: Regular Papers, ISSN 1549-8328, E-ISSN 1558-0806, Vol. 99, 1-10 p.Article in journal (Refereed) Published
This paper presents an analog-to-digital converter (ADC) dedicated to neural recording systems. By using two continuous-time incremental sigma-delta ADCs in a pipeline configuration, the proposed ADC can achieve high-resolution without sacrificing the conversion rate. This two-step architecture is also power-efficient, as the resolution requirement for the incremental sigma-delta ADC in each step is significantly relaxed. To further enhance the power efficiency, a class-AB output stage and a dynamic summing comparator are used to implement the sigma-delta modulators. A prototype chip, designed and fabricated in a standard 0.18 µm CMOS process, validates the proposed ADC architecture. Measurement results show that the ADC achieves a peak signal-to-noise-plus-distortion ratio of 75.9 dB over a 4 kHz bandwidth; the power consumption is 34.8 µW, which corresponds to a figure-of-merit of 0.85 pJ/conv.
Place, publisher, year, edition, pages
2015. Vol. 99, 1-10 p.
Analog-to-digital converter (ADC), incremental sigma-delta ADC, two-step ADC, continuous-time.
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-163179DOI: 10.1109/TCSI.2015.2418892OAI: oai:DiVA.org:kth-163179DiVA: diva2:799049
FunderSwedish Research Council
QC 201505202015-03-282015-03-282015-05-20Bibliographically approved