Design Considerations for Pipelined Continuous-Time Incremental Sigma-Delta ADCs
2015 (English)In: Circuits and Systems (ISCAS), 2015 IEEE International Symposium on, IEEE conference proceedings, 2015, 1014-1017 p.Conference paper (Refereed)
This paper addresses design considerations for power-efficient pipelined continuous-time (CT) incremental Sigma-Delta (IΣ∆) ADC architectures. By pipelining identical CT IΣ∆ ADC stages, the proposed architecture provides the design freedom coming from both the pipeline ADC and the IΣ∆ ADC. In searching for a low-power solution given a target resolution, different configurations are examined analytically and simulated using behavioral models. For further power reduction, power-efficient circuits are proposed to implement the active blocks in each configuration. Based on the architecture-level analysis, a configuration that leads to minimum power-area consumption is chosen and implemented as a test-case using the proposed circuit blocks. Post-layout simulations show that the test-case ADC, with 3.2-kHz bandwidth, achieves a peak SNDR of 82.5-dB while dissipating a total power of 18.27-μW.
Place, publisher, year, edition, pages
IEEE conference proceedings, 2015. 1014-1017 p.
, IEEE International Symposium on Circuits and Systems, ISSN 0271-4302
Other Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-163175DOI: 10.1109/ISCAS.2015.7168808ISI: 000371471001074ScopusID: 2-s2.0-84946217054OAI: oai:DiVA.org:kth-163175DiVA: diva2:799038
IEEE International Symposium on Circuits and Systems (ISCAS),Lisbon, Portugal, May 24 - 27, 2015
FunderSwedish Research Council
QC 201508112015-03-282015-03-282016-04-05Bibliographically approved