Increasing Verilog’s Generative Power
2014 (English)Conference paper (Refereed)
To cope with more complex circuits, well-understood higher-level abstraction mechanisms are needed. Verilog is already equipped with promising generative constructs making it possible to concisely describe a family of circuits as a parameterized module; however these constructs suffer from limited expressivity even in the latest IEEE standard. In this paper, we address generative constructs expressivity limitations, identifying the key extensions needed to overcome these limitations, and showing how to incorporate them in Verilog in a disciplined, backward-compatible way.
Place, publisher, year, edition, pages
IdentifiersURN: urn:nbn:se:hh:diva-27145OAI: oai:DiVA.org:hh-27145DiVA: diva2:767018
DUHDe – 1st Workshop on Design Automation for Understanding Hardware Designs – Workshop at DATE 2014, Dresden, Germany, March 28, 2014
This work was supported by the National Science Foundation (NSF) CPS award 1136099 and the Semiconductor Research Consortium (SRC) Task ID: 1403.001 (Intel custom project).2014-11-282014-11-282015-12-21Bibliographically approved