Worst Case Delay Analysis of a DRAM Memory Request for COTS Multicore Architectures
2014 (English)Conference paper (Refereed)
Dynamic RAM (DRAM) is a source of memory contention and interference problems on commercial of the shelf (COTS) multicore architectures. Due to its variable access time, it can greatly influence the task's WCET and can lead to unpredictability. In this paper, we provide a worst case delay analysis for a DRAM memory request to safely bound memory contention on multicore architectures. We derive a worst-case service time for a single memory request and then combine it with the per-request memory interference that can be generated by the tasks executing on same or different cores in order to generate the delay bound.
Place, publisher, year, edition, pages
Embedded Systems Computer Systems
Research subject Computer Science
IdentifiersURN: urn:nbn:se:mdh:diva-26540OAI: oai:DiVA.org:mdh-26540DiVA: diva2:762573
MCC14, Seventh Swedish Workshop on Multicore Computing, Lund, Nov. 27-28, 2014