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A formal approach to the WCRT analysis of multicore systems with memory contention under phase-structured task sets
Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems. (Embedded Systems)
ETH Zürich.
University of Waterloo.
University of Waterloo.
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2014 (English)In: Real-time systems, ISSN 0922-6443, E-ISSN 1573-1383, Vol. 50, no 5-6, 736-773 p.Article in journal (Refereed) Published
Abstract [en]

Multicore technology has the potential for drastically increasing productivity of embedded real-time computing. However, joint use of hardware, e.g., caches, memory banks and on-chip buses makes the integration of multiple real-time applications into a single system difficult: resource accesses are exclusive and need to be sequenced. Moreover, resource access schemes of modern off-the-shelf multicore chips are commonly optimized for the average-case, rather than being timing predictable. Real-time analysis for such architectures is complex, as execution times depend on the deployed hardware, as well as on the software executing on other cores. This will ask for significant abstractions in the timing analysis, where the resulting pessimism will lead to over-provisioned system designs and a lowered productivity as the number of applications to be put together into a single architecture needs to be decreased. In response to this, (a) we present a formal approach for bounding the worst-case response time of concurrently executing real-time tasks under resource contention and almost arbitrarily complex resource arbitration policies, with a focus on main memory as shared resource, (b) we present a simulation framework which allows for detailed modeling and empirical evaluation of modern multicore platforms and applications running on top of them, and (c) we present experiments to demonstrate the advantages and disadvantages of the presented methodologies and compare their accuracy. For limiting non-determinism inherent to the occurrence of cache misses, we particularly take advantage from the predictable execution model as discussed in recent works.

Place, publisher, year, edition, pages
2014. Vol. 50, no 5-6, 736-773 p.
National Category
Computer Engineering Embedded Systems
Research subject
Computer Science with specialization in Real Time Systems
URN: urn:nbn:se:uu:diva-234343DOI: 10.1007/s11241-014-9211-yISI: 000344182000005OAI: diva2:756276
EU, FP7, Seventh Framework Programme, 288175
Available from: 2014-10-16 Created: 2014-10-16 Last updated: 2014-12-15Bibliographically approved

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