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Transaction Level Modeling of a PCI Express Root Complex
Norwegian University of Science and Technology, Faculty of Information Technology, Mathematics and Electrical Engineering, Department of Electronics and Telecommunications.
2014 (English)MasteroppgaveStudent thesis
Abstract [en]

PCI Express(PCIe) is a packet-based, serial, interconnect standard that is widely deployed within servers and workstations for it's attractive performance capabilities. A platform that has a PCIe architecture also includes a PCIe Root Complex(RC) for linking the PCIe device-tree to the host CPU and memory. During the design-phase of a PCIe endpoint-device it is highly desired to conduct computer aided simulations of the device in a relevant environment. Having a simulation software that can be applied early and iteratively in the design-phase enables engineers to tweak the product without realization of hardware. Causing a great reduction in the number of physical prototypes required before mass production. In this thesis a transaction level model(TLM) of a PCIe RC was assembled using SystemC, with a focus on latency and jitter as performance parameters. The model gives the Application Specific Integrated Circuit(ASIC) developers at Oracle a timing accurate alternative to the existing processor emulator(QEMU) that is used for the same purpose. To correlate the RC TLM with real hardware, a PCIe protocol analyzer from LeCroy was utilized. Traffic between a first generation PCIe endpoint-device and a SUN FIRE X4170 M3 server was traced. The RC TLM was made in a modular manner allowing support for other micro-architectures through insertions of trace files. The recorded traces between requests and completions were processed and inserted directly into a delay database within the RC model, to ensure high correlation between the RC TLM and the real hardware. A simple model of a PCIe endpoint-device was implemented to serve as a suitable test-environment. The functionality and the hardware realisticness of the RC model was successfully tested with targeted transaction scenarios. A simulated latency distribution of 15000 packets, proved to fit the latency distribution that was randomly drawn in the RC TLM. Only a small amount of negligible delay anomalies from imperative switch cycles were found. The PCIe RC TLM is close to optimal for modeling latency and jitter using a database of targeted trace calbrations. The principle of modeling delays in an RC TLM using latency databases, was found to be a favorable alternative to the constant delay nature of the QEMU test-environment.

Place, publisher, year, edition, pages
Institutt for elektronikk og telekommunikasjon , 2014. , 162 p.
URN: urn:nbn:no:ntnu:diva-26506Local ID: ntnudaim:10886OAI: diva2:748315
Available from: 2014-09-18 Created: 2014-09-18 Last updated: 2014-09-18Bibliographically approved

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