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UVM Verification Framework
Norwegian University of Science and Technology, Faculty of Information Technology, Mathematics and Electrical Engineering, Department of Electronics and Telecommunications.
2014 (English)MasteroppgaveStudent thesis
Abstract [en]

The importance of verification is increasing with the size of hardware designs, and reducing the effort required for is necessary to increase productivity. This thesis covers the creation of a reusable verification framework for processor verification using the Universal Verification Methodology (UVM). The framework is used to verify three simple processor designs to evaluate its potential for reuse. The three processors include a synchronous, asynchronous and a stack based processor. A pure UVM implementation is evaluated against the use of external checking by Assertion Based Verification (ABV), which is found to provide a better overview. The framework is shown to be highly reusable, especially for input generation, and can be used for both synchronous and asynchronous design. The high reusability is a key part of increasing productivity gained by removal of redundant work. This framework is intended as a proof of concept, and is does not provide a complete verification for each of the designs.

Place, publisher, year, edition, pages
Institutt for elektronikk og telekommunikasjon , 2014. , 58 p.
URN: urn:nbn:no:ntnu:diva-26298Local ID: ntnudaim:11389OAI: diva2:746147
Available from: 2014-09-11 Created: 2014-09-11 Last updated: 2014-09-11Bibliographically approved

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