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A Framework for Characterizing Predictable Platform Templates
KTH, School of Information and Communication Technology (ICT), Electronic Systems.ORCID iD: 0000-0002-2171-1528
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
KTH, School of Information and Communication Technology (ICT), Electronic Systems.ORCID iD: 0000-0003-4859-3100
2014 (English)Report (Other academic)
Abstract [en]

The design of real-time multiprocessor systems is a very costly and time-consuming process due to the need for extensive verification efforts. Genericcorrect-by-construction system-level design flows, targeting predictable plat-forms, would help to tackle this problem. Unfortunately, because system-level design problems are formulated monolithically, existing methods areeither not powerful enough to perform efficient design space exploration,over-customized to a specific class of platforms, or do not allow to be ex-tended with new heuristics and solving methods, which makes their reusedifficult. We present a formal framework to explicitly capture and character-ize predictable platform templates that can be used to formulate a genericdesign flow for real-time streaming applications in a composable manner. Aproof-of-concept implementation of such a flow is performed and used to mapa JPEG encoder application onto an FPGA-based time-predictable platform.

Place, publisher, year, edition, pages
Stockholm, Sweden: KTH Royal Institute of Technology, 2014. , 18 p.
Series
TRITA-ICT/ECS R, ISSN 1653-7238 ; 14:01
Keyword [en]
automation, design-space exploration, predictable platforms, real-time systems
National Category
Embedded Systems
Identifiers
URN: urn:nbn:se:kth:diva-148162ISRN: KTH/ICT/ECS/R-14-01-SEOAI: oai:DiVA.org:kth-148162DiVA: diva2:735860
Note

QC 20140819

Available from: 2014-08-01 Created: 2014-08-01 Last updated: 2014-11-17Bibliographically approved
In thesis
1. Managing the Complexity in Embedded and Cyber-Physical System Design: System Modeling and Design-Space Exploration
Open this publication in new window or tab >>Managing the Complexity in Embedded and Cyber-Physical System Design: System Modeling and Design-Space Exploration
2014 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

To cope with the increasing complexity of embedded and cyber-physical system design, different system-level design approaches are proposed which start from abstract models and implement them using design flows with high degrees of automation. However, creating models of such systems and also formulating the mathematical problems arising in these design flows are themselves challenging tasks. A promising approach is the composable construction of these models and problems from more basic entities. Unfortunately, it is non-trivial to propose such compositional formulations today because the current practice in the electronic design automation domain tends to be on using imperative languages and frameworks due to legacy and performance-oriented reasons.

This thesis addresses the system design complexity by first promoting proper formalisms and frameworks for capturing models and formulating design-space exploration problems for electronic system-level design in a declarative style; and second, propose realizations based on the industrially accepted languages and frameworks which hold the interesting properties such as composability and parallelism.

For modeling, ForSyDe, a denotational system-level modeling formalism for heterogeneous embedded systems is chosen, extended with timed domains to make it more appropriate for capturing cyber-physical systems, and mapped on top of the IEEE standard system design language SystemC. The realized modeling framework, called ForSyDe-SystemC, can be used for modeling systems of heterogeneous nature and their composition to form more sophisticated systems and also conducting parallel and distributed simulation for boosting the simulation speed. Another extension to ForSyDe, named wrapper processes, introduces the ability to compose formal ForSyDe models with legacy IP blocks running in external execution environments to perform a heterogeneous co-simulation.

In platform-based design flows, the correct and optimal mapping of an application model onto a flexible platform involves solving a hard problem, named design space exploration. This work proposes Tahmuras, a constraint- based framework to construct generic design space exploration problems as the composition of three individual sub-problems: the application, the platform, and the mapping and scheduling problems. In this way, the model of the design space exploration problem in Tahmuras is automatically generated for each combination of application semantics, target platform, and mapping and scheduling policy simply by composing their respective problems. Using constraint programming, problems can be modeled in a declarative style, while they can be solved in a variety of different styles, including imperative solving heuristics commonly used to solve difficult problems. Efficient parallel solvers exists for constraint programming. 

Abstract [sv]

Den ökande komplexiteten är en stor utmaning för konstruktionen av framtida inbyggda system. För att möta utmaningen utvecklas nu konstruktionsmetoder som har som mål att starta från en abstrakt modell och att generera en implementering genom ett konstruktionsflöde med hög automatiseringsgrad. Dessvärre är dock skapandet av abstrakta systemmodeller och formaliseringen av de relaterade matematiska problemen i sig ett mycket utmanande problem. Konstruktion genom komposition av basenheter är en lovande idé, men tyvärr är det väldigt svårt att introducera metoden i dagens industriella konstruktionsflöden på grund av imperativa programmeringsspråk och ett gammalt arv i form av existerande kodbas och äldre konstruktioner.

Avhandlingen adresserar komplexiten inom systemkonstruktion genom att föreslå passande formalismer för att uttrycka modeller i en deklarativ stil och angripa problemet att hitta en passande implementering. Dessutom visar avhandlingen hur dessa formalismer kan realiseras i en form som kan användas i ett industriellt sammanhang utan att förlora formalismens viktiga grundläggande egenskaper som komposition och parallelism.

Modelleringen använder och utökar ForSyDe, en konstruktionsmetod för heterogena inbyggda system. Tilläggen består av en modelleringsmodell som kan fånga specifika egenskaper hos heterogena inbyggda system, samt en implementering av ForSyDe i SystemC, ett industriellt modelleringsspråk som är standardiserat av IEEE. Den nya utvecklingsmiljön, ForSyDe-SystemC, kan användas för att modellera inbyggda system, komponera systemmodeller till större system, samt möjliggör genomförandet av parallella och distribuerade simuleringar med medföljande hög simuleringshastighet. Avhandlingen introducerar också “wrapper”-konceptet i ForSyDe som möjliggör integrationen av existerande modeller och system som en del av en formell ForSyDe-modell och deras co-simulering. ForSyDe-SystemC har använts inom EU-projekt av industriella partner för modellering av egna system.

Att hitta en korrekt och effektiv implementering av en abstrakt systemmodell är målet inom aktiviteten “design space exploration” (DSE) som är ett svårt problem för parametriserbara och flexibla plattformar. Avhandlingen presenterar två generationer av Tahmuras, som är baserade på villkorsprogrammering och har som mål att konstruera DSE-problemet som en komposition av tre olika delproblem: applikation, plattform, och bindning. Ett integrerat DSE-problem kan sedan automatiskt genereras genom en kombination av dessa delproblem. Olika metoder, från heuristisk till komplett sökning, kan användas inom villkorsprogrammering för att lösa DSE-problemet. För att visa Tahmuras potential har DSE-metoden validerats med hjälp av olika systemapplikationer av skilda tidsegenskaper och olika plattformar. 

Place, publisher, year, edition, pages
Stockholm: KTH Royal Institute of Technology, 2014. xvi, 104 p.
Series
TRITA-ICT-ECS AVH, ISSN 1653-6363 ; 14:12
National Category
Embedded Systems
Identifiers
urn:nbn:se:kth:diva-155939 (URN)978-91-7595-286-4 (ISBN)
Public defence
2014-12-05, Sal B, Electrum 229, KTH-ICT, Kista, 13:00 (English)
Opponent
Supervisors
Note

QC 20141117

Available from: 2014-11-17 Created: 2014-11-15 Last updated: 2014-11-17Bibliographically approved

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