Change search
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf
Power Savings in MPSoC
KTH, School of Information and Communication Technology (ICT).
2009 (English)Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
Abstract [en]

High performance integrated circuits suffer from a permanent increase of the dissipated power per square millimeter of silicon, over the past years. This phenomenon is driven by the miniaturization of CMOS processes, increasing packing density of transistors and increasing clock frequencies of microchips, thus pushing heat removal and power distribution to the forefront of the problems confronting the advance of microelectronics. In the opposite direction is the market growth of mainstream portable devices, which require extremely low power consumption. These evolving factors brought power dissipation into play and transformed it into a major design metric. This thesis comprises those knowledge and methodological tools that can offer a preliminary safe path toward less power-hungry SoC and MPSoC designs, thus contributing towards a holistic approach of power-related effects.

This is accomplished by providing the essential theoretical background of CMOS power dissipation, investigating a vast range of power saving techniques and plotting their classifications, according to the power components each technique is meant to suppress and, the level of abstraction that it can be applied at, thus facilitating proper decision making about which power saving techniques to apply on a certain design. Moreover, this thesis implements, demonstrates and evaluates generic power analysis and optimization flows that are based on the ASIC industry’s de facto standard Synopsys tools. The tools’ actual capabilities are contrasted to the theoretical expectations and the chief tradeoffs that are involved in terms of speed versus accuracy and attainable power savings versus abstraction level are stressed. Our extracted power results, for an Ericsson’s large ASIC block, show that by putting emphasis on coping with power early, thus enhancing typical synthesis flows with an appropriate set of techniques, significant savings can be achieved for both dynamic and static power components in the front-end synthesis domain.

Place, publisher, year, edition, pages
2009. , 92 p.
Series
TRITA-ICT-EX, 2009:158
National Category
Computer and Information Science
Identifiers
URN: urn:nbn:se:kth:diva-147365OAI: oai:DiVA.org:kth-147365DiVA: diva2:729889
Subject / course
Electronic- and Computer Systems
Educational program
Master of Science - System-on-Chip Design
Examiners
Available from: 2014-06-26 Created: 2014-06-26 Last updated: 2014-06-26Bibliographically approved

Open Access in DiVA

fulltext(2385 kB)359 downloads
File information
File name FULLTEXT01.pdfFile size 2385 kBChecksum SHA-512
45d11616fae14253bc910e5e1e9d01ab0cfc2d7c4045870f3505d29ee477ea39de047432d968bcec981dceed1b556d2ba33808b9eacd2cde194aed6205d637a3
Type fulltextMimetype application/pdf

By organisation
School of Information and Communication Technology (ICT)
Computer and Information Science

Search outside of DiVA

GoogleGoogle Scholar
Total: 359 downloads
The number of downloads is the sum of all downloads of full texts. It may include eg previous versions that are now no longer available

urn-nbn

Altmetric score

urn-nbn
Total: 118 hits
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf