FFT Hardware Architectures with Reduced Twiddle Factor Sets
Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
The goal of this thesis has been to reduce the hardware cost of SDF FFTs. Inorder to achieve this, two methods for simplifying rotations in FFTs are presented:Decimation and Reduction. When applied, these methods reduce the total amountof angles that the rotators need to rotate, as well as the total angle count of theFFT. This is useful for constant shift and add based rotators, as their hardwarecost are typically dependent on the amount of angles it needs to calculate.Decimation works by splitting a large twiddle factor into a smaller one plusan additional small rotator in series. This allows for the possibility to implementlarge FFTs without needing any large twiddle factors. Reduction is a method thattakes a twiddle factor and simplifies it by removing one angle from the rotator.This can be done without adding any hardware cost if applied correctly.In addition to the methods, the thesis also includes proposed designs for 64- upto 1024-point FFTs, as well as post-implementation results for a 32- and 64-pointFFT.
Place, publisher, year, edition, pages
2013. , 64 p.
Engineering and Technology
IdentifiersURN: urn:nbn:se:liu:diva-108148ISRN: LiTH-ISY-EX--13/4731--SEOAI: oai:DiVA.org:liu-108148DiVA: diva2:729491
Subject / course
Garrido, Mario, Associate Professor
Gustafsson, Oscar, Docent