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Event System Implementations for Microcontroller Circuits
Norwegian University of Science and Technology, Faculty of Information Technology, Mathematics and Electrical Engineering, Department of Electronics and Telecommunications.
2009 (English)MasteroppgaveStudent thesis
Abstract [en]

To ensure effective peripheral communication on their new AVR® XMEGA microcontroller platform, Atmel has included a peripheral resource known as an Event System. Through the submitted research from this thesis, new solutions for Event System implementations have been investigated and a selected solution has been has been designed in Verilog and synthesized for the Xilinx Spartan 3 XC3S1000 FPGA. To find inspiration for developing new and cost effective Event System solutions with programmability features, an extensive literature study in the fields of FPGA related design and asynchronous circuit design was accompliced. After proposing two Event System solutions featuring programmable routing with a centralized I/O-processor and CPLD-elements, a decision was made to focus on an asynchronous Event System solution. Interesting features like a pipelined high-speed interconnect structure and possibilities for power saving due to natural power down capabilities where two of the reasons for this focus. Another factor was the academic value of researching if a programmable asynchronous routing structure was applicable for microcontroller implementation, and especially to see if such an implementation could be realistic and beneficial for the AVR® XMEGA or AVR®32. Increased asynchronous focus made it a natural choice to restrict the work towards physical FPGA implementation in order to provide a thorough research and develop a good Asynchronous Event System model. The first focus for each of the proposed Event System solutions was to develop a new and cost effective routing facility, designing custom switch elements to fit the developed programmable FPGA inspired routing topology. After giving increased attention to the Asynchronous Event System, LUT elements implemented in an asynchronous handshake environment was included to perform logical computations on events. By reusing elements from existing peripherals to include and interconnect LUTs, a powerful computation environment was introduced. To verify the Asynchronous Event System model and featured asynchronous principles, a Verilog model of the Asynchronous Event System Routing Network including global and local routing resources and a custom asynchronous LUT for event computation was designed. Simulation results verify the Asynchronous Event System model’s behavior, and give notions on the system capacity. Synthesis towards the Xilinx Spartan 3 XC3S1000 FPGA was done to check physical implementation size, and make sure a synthesizable design was developed. Estimated area results approximates an asynchronous Event System to about 5555 NAND gate equivalents without computational LUT elements, and from 6418 NAND equivalents with 2 interconnected 4-LUTs to 11413 NAND gates with a full range of 24 interconnected 4-LUTs. Size increase compared to the current Event System is 23% larger for a non-computational version, and from 43% to 154% larger for 2 and 24 included 4-LUTs respectively. Included in the size increase is programmable routing demanding 924 bits for global and local routing only, and 1724 bits for full programmability with 24 4-LUTs. Simulations show a possibility for transporting up to 32 events concurrently, which is an increase of four times the current Event System capacity. Performance evaluations put the developed Asynchronous Event System from 6.5 – 1.6 times faster than the current Event System estimated for 90nm – 350nm processes. Considering HERN area estimations, a simple I/O-processor alternative consumes 3150 NAND gates included programmable routing. A CERN solution featuring one CPLD MCB for each Port / TC peripheral requires 5308 NAND equivalents. All area estimations are based on developed architectural drawings, and are estimated according to the Atmel’s 35k9 in-house process, thereby not representing a synthesized result.

Place, publisher, year, edition, pages
Institutt for elektronikk og telekommunikasjon , 2009. , 146 p.
URN: urn:nbn:no:ntnu:diva-24986Local ID: ntnudaim:4733OAI: diva2:727318
Available from: 2014-06-19 Created: 2014-06-19 Last updated: 2014-06-19Bibliographically approved

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