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Energy Efficient Wireless Sensor Node Architecture for Data and Computation Intensive Applications
Mid Sweden University, Faculty of Science, Technology and Media, Department of Electronics Design.ORCID iD: 0000-0002-3493-7016
2014 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

Wireless Sensor Networks (WSNs), in addition to enabling monitoring solutions for numerous new applications areas, have gained huge popularity as a cost-effective, dynamically scalable, easy to deploy and maintainable alternatives to conventional infrastructure-based monitoring solutions.

A WSN consists of spatially distributed autonomous wireless sensor nodes that measure desired physical phenomena and operate in a collaborative manner to relay the acquired information wirelessly to a central location. A wireless sensor node, integrating the required resources to enable infrastructure-less distributed monitoring, is constrained by its size, cost and energy. In order to address these constraints, a typical wireless sensor node is designed based on low-power and low-cost modules that in turn provide limited communication and processing performances. Data and computation intensive wireless monitoring applications, on the other hand, not only demand higher communication bandwidth and computational performance but also require practically feasible operational lifetimes so as to reduce the maintenance cost associated with the replacement of batteries. In relation to the communication and processing requirements of such applications and the constraints associated with a typical wireless sensor node, this thesis explores energy efficient wireless sensor node architecture that enables realization of data and computation intensive applications.

Architectures enabling raw data transmission and in-sensor processing with various technological alternatives are explored. The potential architectural alternatives are evaluated both analytically and quantitatively with regards to different design parameters, in particular, the performance and the energy consumption. For quantitative evaluation purposes, the experiments are conducted on vibration and image-based industrial condition monitoring applications that are not only data and computation intensive but also are of practical importance.

Regarding the choice of an appropriate wireless technology in an architecture enabling raw data transmission, standard based communication technologies including infrared, mobile broadband, WiMax, LAN, Bluetooth, and ZigBee are investigated. With regards to in-sensor processing, different architectures comprising of sequential processors and FPGAs are realized to evaluate different design parameters, especially the performance and energy efficiency. Afterwards, the architectures enabling raw data transmission only and those involving in-sensor processing are evaluated so as to find an energy efficient solution. The results of this investigation show that in-sensor processing architecture, comprising of an FPGA for computation purposes, is more energy efficient when compared with other alternatives in relation to the data and computation intensive applications.

Based on the results obtained and the experiences learned in the architectural evaluation study, an FPGA-based high-performance wireless sensor platform, the SENTIOF, is designed and developed. In addition to performance, the SETNIOF is designed to enable dynamic optimization of energy consumption. This includes enabling integrated modules to be completely switched-off and providing a fast configuration support to the FPGA.

 In order to validate the results of the evaluation studies, and to assess the performance and energy consumption of real implementations, both the vibration and image-based industrial monitoring applications are realized using the SENTIOF. In terms of computational performance for both of these applications, the real-time processing goals are achieved. For example, in the case of vibration-based monitoring, real-time processing performance for tri-axes (horizontal, vertical and axial) vibration data are achieved for sampling rates of more than 100 kHz.

With regards to energy consumption, based on the measured power consumption that also includes the power consumed during the FPGA’s configuration process, the operational lifetimes are estimated using a single cell battery (similar to an AA battery in terms of shape and size) with a typical capacity of 2600 mA. In the case of vibration-based condition monitoring, an operational lifetime of more than two years can be achieved for duty-cycle interval of 10 minutes or more. The achievable operational lifetime of image-based monitoring is more than 3 years for a duty-cycle interval of 5 minutes or more. 

Place, publisher, year, edition, pages
Sundsvall, Sweden: Mid Sweden University , 2014. , 112 p.
Series
Mid Sweden University doctoral thesis, ISSN 1652-893X ; 192
Keyword [en]
WSN, wireless sensor node, architecture, vibration monitoring, image monitoring, energy efficient, FPGA, power management, embedded system
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:miun:diva-21956ISBN: 978-91-87557-64-4 (print)OAI: oai:DiVA.org:miun-21956DiVA: diva2:719439
Public defence
2014-06-11, M102, Sundsvall, 10:15 (English)
Opponent
Supervisors
Available from: 2014-05-26 Created: 2014-05-24 Last updated: 2017-10-27Bibliographically approved
List of papers
1. Feasibility study of on-Rotor Vibration Monitoring using Accelerometers
Open this publication in new window or tab >>Feasibility study of on-Rotor Vibration Monitoring using Accelerometers
(English)Manuscript (preprint) (Other academic)
Abstract [en]

Vibration based condition monitoring is the most widely accepted method for determining the defects and the performance degradation of rotating machinery. Common practices for monitoring vibration involve employing a displacement transducer for the rotor and an accelerometer for the stator. This paper presents a novel architecture for on-rotor vibration measurement based on accelerometers, and a high sampling rate vibration monitoring sensor node with analysis capability. A detailed analysis of the technological challenges and bottlenecks including bandwidth, wireless communication, processing capabilities and energy consumption of the proposed architecture are discussed. The experimental results of the rotor and the stator vibration are compared and are presented.   

Keyword
Vibration monitoring, on-rotor vibration monitoring, wireless vibration monitoring system
National Category
Engineering and Technology
Identifiers
urn:nbn:se:miun:diva-21102 (URN)
Available from: 2014-01-21 Created: 2014-01-21 Last updated: 2017-10-27Bibliographically approved
2. A comparative study of raw data transmission using ZigBee, BLE and Wi-Fi vs. in-sensor processing for data intensive monitoring applications
Open this publication in new window or tab >>A comparative study of raw data transmission using ZigBee, BLE and Wi-Fi vs. in-sensor processing for data intensive monitoring applications
(English)Manuscript (preprint) (Other academic)
Abstract [en]

Wireless sensor nodes, as typically realized using IEEE 802.15.4 compatible low-power radio transceivers that offer limited throughput, are generally applicable to low-data rate intermittent monitoring applications. In order to realize high sample rate monitoring applications, it either requires transmitting raw data using a high-throughput radio transceiver or performing computation within the sensor node and then transmitting small amount of information. In relation energy constrained wireless sensing node, a quantitative evaluation of raw data transmission using different short range wireless technologies and in-sensor processing is carried out in this paper. The results, associated with the energy consumption of two data intensive monitoring applications, suggest that in-sensor processing resulting in small amount of transmission data consume less energy as compared to that of raw data transmission under ideal channel conditions.

Keyword
ZigBee; Bluetooth low energy; BLE; IEEE 802.15.4; Wi-Fi; in-sensor processing; wireless sensor;
National Category
Engineering and Technology
Identifiers
urn:nbn:se:miun:diva-21100 (URN)
Available from: 2014-01-21 Created: 2014-01-21 Last updated: 2017-10-27Bibliographically approved
3. Architecture exploration for a high-performance and low-power wireless vibration analyzer
Open this publication in new window or tab >>Architecture exploration for a high-performance and low-power wireless vibration analyzer
2013 (English)In: IEEE Sensors Journal, ISSN 1530-437X, E-ISSN 1558-1748, Vol. 13, no 2, 670-682 p.Article in journal (Refereed) Published
Abstract [en]

Vibration based condition monitoring is considered to be the most effective method for analyzing the performance of rotating machinery and for early fault detection. Traditional vibration analyzers used for this purpose provide wired interface(s) to connect sensors with the system that analyzes the vibration data. A wireless vibration analyzer can be useful to monitor and analyze the vibration of rotating as well as inaccessible parts of the machinery. However, for a wireless vibration analyzer, both the performance and power consumption are of major concern, especially for real-time tri-axes (horizontal, vertical, and axial) vibration data processing and analyses at a high sampling rate. To evaluate the performance of such an analyzer, we explore different architectures in order to realize a high-performance and low-power wireless vibration analyzer that can be used in addition to traditional analyzers. For this purpose, four different architectures have been implemented in order to evaluate them in terms of performance, power consumption, cost, and design complexity.

Keyword
Field programmable gate array (FPGA) and micro-controller based analyzer; hardware architecture; low-power analyzer; wireless vibration monitoring
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:miun:diva-17892 (URN)10.1109/JSEN.2012.2226238 (DOI)000313876800008 ()2-s2.0-84873170342 (Scopus ID)STC (Local ID)STC (Archive number)STC (OAI)
Note

Published online: 24 October 2012

Available from: 2012-12-18 Created: 2012-12-18 Last updated: 2017-10-27Bibliographically approved
4. Investigating Energy Consumption of an SRAM-based FPGA for Duty-Cycle Applications
Open this publication in new window or tab >>Investigating Energy Consumption of an SRAM-based FPGA for Duty-Cycle Applications
2014 (English)In: Advances in parallel computing, 2014, 548-559 p.Conference paper, Published paper (Refereed)
Abstract [en]

In order to conserve energy, battery powered embedded systems are typically designed with very low-power modules that offer limited computational power and communication bandwidth and therefore, are generally applicable to low-sample-rate intermittent applications. On the other hand, enabling an embedded system with a high-throughput processing resource such as an FPGA, high-throughput processing performance that is typically required in high-sample rate monitoring applications can be achieved. However, the high power consumption associated with an FPGA poses a major challenge in attaining significant lifetime for a battery-powered embedded system. In this paper, we investigate energy consumption of an SRAM-based FPGA in relation to duty-cycle applications. In order to achieve long operational lifetime in an FPGA-based embedded system, the possible options to dynamically manage the power consumption are studied and discussed. The experimental results suggest that the SRAM-based FPGA, XC6SLX16 that provides ample logic resources in relation to typical high-sample rate monitoring applications, can be used in a battery operated embedded systems while minimizing the energy consumption to 2.56 mJ for inactive duration of 235 ms or above.

Keyword
Energy optimization; SRAM-based FPGA; High-sample rate; Dynamic power management; Duty-cycling
National Category
Engineering and Technology
Identifiers
urn:nbn:se:miun:diva-21093 (URN)10.3233/978-1-61499-381-0-548 (DOI)2-s2.0-84902282682 (Scopus ID)STC (Local ID)978-1-61499-380-3 (ISBN)STC (Archive number)STC (OAI)
Conference
International Conference on Parallel Computing - ParCo 2013, 10-13 Sept, Munich
Available from: 2014-01-21 Created: 2014-01-21 Last updated: 2017-10-27Bibliographically approved
5. SENTIOF: An FPGA based high-performance and low-power wireless embedded platform
Open this publication in new window or tab >>SENTIOF: An FPGA based high-performance and low-power wireless embedded platform
2013 (English)In: 2013 Federated Conference on Computer Science and Information Systems, FedCSIS 2013: Proceedings, IEEE conference proceedings, 2013, 901-906 p.Conference paper, Published paper (Refereed)
Abstract [en]

Traditional wireless sensor nodes are designed with low-power modules that offer limited computational performance and communication bandwidth and therefore, are generally applicable to low-sample rate intermittent monitoring applications. Nevertheless, high-sample rate monitoring applications can be realized by designing sensor nodes that can perform high-throughput in-sensor processing, while maintaining low-power characteristics. In this paper, a high-performance and low-power wireless hardware platform is presented. With its compact size and modular structure enabling there to be an integrated customized sensor layer, it can be used for a wide variety of applications. In addition, the flexibility provided through dynamically configurable interfaces and power management, helps optimizing performance and power consumption for different applications.

Place, publisher, year, edition, pages
IEEE conference proceedings, 2013
Keyword
FPGA, wireless platform, high-throughput, low-power
National Category
Engineering and Technology
Identifiers
urn:nbn:se:miun:diva-21092 (URN)000347171500146 ()2-s2.0-84892498747 (Scopus ID)978-1-4673-4471-5 (ISBN)
Conference
2013 Federated Conference on Computer Science and Information Systems, FedCSIS 2013; Krakow; Poland; 8 September 2013 through 11 September 2013; Category numberCFP1385N-ART; Code 102014
Available from: 2014-01-21 Created: 2014-01-21 Last updated: 2017-10-27Bibliographically approved
6. An FPGA-Based High-Performance Wireless Vibration Analyzer
Open this publication in new window or tab >>An FPGA-Based High-Performance Wireless Vibration Analyzer
2013 (English)In: NORCHIP 2013, 2013, Art. no. 6702038- p.Conference paper, Published paper (Refereed)
Abstract [en]

In this article, an Field Programmable Gate Array (FPGA) based high-performance wireless vibration analyzer that performs high sample rate tri-axes (horizontal, vertical, and axial) vibration monitoring and analysis, is presented. The custom designed compact size wireless analyzer can be mounted on difficult to access as well as rotating parts of the machinery so as to perform vibration based condition monitoring. Based on the measured performance and power consumption, the analyzer not only achieves the performance goals for high-sample rate (i.e. at 50 kHz) tri-axes vibration data processing but, also achieves operational lifetime of more than three years for duty-cycle durations of more than 4 hours.

Keyword
wireless vibration analyzer, FPGA, local processing, high-sample rate, high-performance, low-power
National Category
Engineering and Technology
Identifiers
urn:nbn:se:miun:diva-21095 (URN)10.1109/NORCHIP.2013.6702038 (DOI)000345902700042 ()2-s2.0-84893632589 (Scopus ID)978-1-4799-1647-4 (ISBN)
Conference
NORCHIP 2013; Vilnius; Lithuania; 11 November 2013 through 12 November 2013; Category numberCFP13828-ART; Code 102495
Available from: 2014-01-21 Created: 2014-01-21 Last updated: 2017-10-27Bibliographically approved
7. Quantitative Evaluation of an FPGA based Wireless Vibration Monitoring System in relation to Different Sampling Rates
Open this publication in new window or tab >>Quantitative Evaluation of an FPGA based Wireless Vibration Monitoring System in relation to Different Sampling Rates
2014 (English)In: Proceedings of the International Conference on Sensing Technology, ICST, IEEE Computer Society, 2014, Vol. 2014, 510-516 p.Conference paper, Published paper (Refereed)
Abstract [en]

In order to achieve the high-processing performance  required in typical computationally intensive high-sample rate monitoring applications, a Field Programmable Gate Array (FPGA) is often used as a hardware accelerator.  Given the design complexity, increased power consumption and additional cost of an FPGA, it is desirable to determine the sampling rates for which the use of an FPGA as hardware accelerator results in most effective solution. For this purpose, a computationally intensive application is realized on an FPGA based architecture so as to determine the sampling rates for which it achieves the highest performance and consumes the least amount of energy as compared to that of a micro-controller based architecture. Based on the measured performance and energy consumption for a computationally intensive application, tri-axes/three-channel vibration based condition monitoring, the results suggest that the FPGA based architecture is the most appropriate solution for sampling frequencies of 4 kHz and above.

Place, publisher, year, edition, pages
IEEE Computer Society, 2014
Keyword
wireless monitoring, FPGA, sampling rate, high-sample rate, energy consumption, hardware accelerator
National Category
Engineering and Technology
Identifiers
urn:nbn:se:miun:diva-21098 (URN)2-s2.0-84978516362 (Scopus ID)
Conference
8th International Conference on Sensing Technology, ICST 2014; Liverpool; United Kingdom; 2 September 2014 through 4 September 2014
Available from: 2014-01-21 Created: 2014-01-21 Last updated: 2017-10-27Bibliographically approved
8. Energy Efficient SRAM FPGA based Wireless Vision Sensor Node: SENTIOF‐CAM
Open this publication in new window or tab >>Energy Efficient SRAM FPGA based Wireless Vision Sensor Node: SENTIOF‐CAM
Show others...
2014 (English)In: IEEE transactions on circuits and systems for video technology (Print), ISSN 1051-8215, E-ISSN 1558-2205, Vol. 24, no 12, 2132-2143 p.Article in journal (Refereed) Published
Abstract [en]

Many Wireless Vision Sensor Networks (WVSNs) applications are characterized to have a low duty cycling. An individual wireless Vision Senor Node (VSN) in WVSN is required to operate with limited resources i.e., processing, memory and wireless bandwidth on available limited energy. For such resource constrained VSN, this paper presents a low complexity, energy efficient and programmable VSN architecture based on a design matrix which includes partitioning of processing load between the node and a server, a low complexity background subtraction, bi-level video coding and duty cycling. The tasks partitioning and proposed background subtraction reduces the processing energy and design complexity for hardware implemented VSN. The bi-level video coding reduces the communication energy whereas the duty cycling conserves energy for lifetime maximization. The proposed VSN, referred to as SENTIOF-CAM, has been implemented on a customized single board, which includes SRAM FPGA, microcontroller, radio transceiver and a FLASH memory. The energy values are measured for different states and results are compared with existing solutions. The comparison shows that the proposed solution can offer up to 69 times energy reduction. The lifetime based on measured energy values shows that for a sample period of 5 minutes, a 3.2 years lifetime can be achieved with a battery of 37.44 kJ energy. In addition to this, the proposed solution offers generic architecture with smaller design complexity on a hardware reconfigurable platform and offers easy adaptation for a number of applications.

Keyword
Architecture, image coding, SRAM field-programmable gate array (FPGA), wireless vision sensor networks (WVSNs), wireless vision sensor node (VSN
National Category
Engineering and Technology
Identifiers
urn:nbn:se:miun:diva-21103 (URN)10.1109/TCSVT.2014.2330660 (DOI)000346150200010 ()2-s2.0-84916934186 (Scopus ID)STC (Local ID)STC (Archive number)STC (OAI)
Available from: 2014-01-21 Created: 2014-01-21 Last updated: 2017-10-27Bibliographically approved

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