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Metal Filling of Through Silicon Vias (TSVs) using Wire Bonding Technology
KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
2014 (English)Independent thesis Advanced level (professional degree), 20 credits / 30 HE creditsStudent thesis
Abstract [en]

Through Silicon Vias (TSVs) are vertical interconnections providing the shortest possible signal paths between vertically stacked chips in 3D packaging. In this thesis, TSVs are fabricated and two novel approaches for the metal filling of TSVs are investigated. A wire bonder is utilized to apply TSV core material in the form of gold stud bumps. The metal filling approaches are carried out by 1) squeezing stud bumps down the TSV holes by utilizing a wafer bonder and 2) stacking stud bumps on the outer periphery of the TSV holes and thereby forcing the material further down. Both approaches have successfully filled TSV holes of varying depths and no voids have been observed. The squeezing approach reaches measured depths of up to 52.9 μm and the stacking approach reaches depths of up to 100 μm.

Place, publisher, year, edition, pages
2014.
Series
EES Examensarbete / Master Thesis
Keyword [en]
Through Silicon Vias, TSV, wire bonding
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-145552OAI: oai:DiVA.org:kth-145552DiVA: diva2:718812
Educational program
Master of Science in Engineering - Microelectronics
Supervisors
Examiners
Available from: 2014-07-14 Created: 2014-05-22 Last updated: 2014-07-14Bibliographically approved

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