Soft-Supply Inverter: A New Power-Saving Logical Gate Applied in Several Sub-Modules of a 9-bit 1kS/s SAR ADC
A new double-input-single-output logical gate called soft-supply inverter (SSI) has been presented here in this report. Simulations of the gate reveals a 25% lower static power consumption and a 100% higher dynamic power consumption, compared to standard logical equivalent design. Thus, the design was chosen to be a simulated as a part of the digital control logic in a 1kS/s 9-bit successive approximation register analog-to-digital converter (SAR ADC).
New versions of the D-latch, D-Flip Flop (DFF), 4-1 mux and additional reset circuitry has been designed using the SSI. Also, the C2MOS and PowerPC 603 latches were used as both latches and flip-flops in order to compare with the SSI as alternative solutions of the same design.
A literature study was performed where the designs of  and  were considered the current state-of-the-art SAR ADCs for group-A converters. Because  aims at the comparator, which is outside the scope of this paper,  was chosen as the basis for the digital part of this work.
Simulations revealed a large reduction in power consumption, compared to standard logic design. The state machine, which was mostly DFF-based, revealed a 40% reduction in power consumption with the use of the SSI latch and DFF. However, the C2MOS and PowerPC 603 versions revealed an even further reduction by as much as 64%. Regardless, the reset circuitry for these alternate designs showed a 14% and 20% decrease in power consumption, respectively, when the SSI was applied.
Place, publisher, year, edition, pages
Institutt for elektronikk og telekommunikasjon , 2014. , 96 p.
IdentifiersURN: urn:nbn:no:ntnu:diva-24685Local ID: ntnudaim:9920OAI: oai:DiVA.org:ntnu-24685DiVA: diva2:717015
Ytterdal, Trond, ProfessorAunet, Snorre