Change search
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf
Integration of thulium silicate for enhanced scalability of high-k/metal gate CMOS technology
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.ORCID iD: 0000-0003-0333-376X
2014 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

High-k/metal gate stacks have been introduced in CMOS technology during the last decade in order to sustain continued device scaling and ever-improving circuit performance. Starting from the 45 nm technology node, the stringent requirements in terms of equivalent oxide thickness and gate current density have rendered the replacement of the conventional SiON/poly-Si stack unavoidable. Although Hf-based technology has become the de facto industry standard for high-k/metal gate MOSFETs, problematic long-term scalability has motivated the research of novel materials and solutions to fulfill the target performances expected of gate stacks in future technology nodes.

In this work, integration of a high-k interfacial layer has been identified as the most promising approach to improve gate dielectric scalability, since this technology presents the advantage of potential compatibility with both current Hf-based and plausible future higher-k materials. Thulium silicate has been selected as candidate material for integration as interfacial layer, thanks to its unique properties which enabled the development of a straightforward integration process achieving well-controlled and repeatable growth in the sub-nm thickness regime, a contribution of 0.25+-0.15 nm to the total EOT, and high quality of the interface with Si.

Compatibility with industry-standard CMOS integration flows has been kept as a top priority in the development of the new technology. To this aim, a novel ALD process has been developed and characterized, and a manufacturable process flow for integration of thulium silicate in a generic gate stack has been designed. The thulium silicate interfacial layer technology has been verified to be compatible with standard integration flows, and fabrication of high-k/metal gate MOSFETs with excellent electrical characteristics has been demonstrated.

The possibility to achieve high performance devices by integration of thulium silicate in current Hf-based technology has been specifically demonstrated, and the TmSiO/HfO2 dielectric stack has been shown to be compatible with the industrial requirements of operation in the sub-nm EOT range (down to 0.6 nm), reliable device operation over a 10 year expected lifetime, and compatibility with common threshold voltage control techniques. The thulium silicate interfacial layer technology has been especially demonstrated to be superior to conventional chemical oxidation in terms of channel mobility at sub-nm EOT, since the TmSiO/HfO2 dielectric stack achieved ~20% higher electron and hole mobility compared to state-of-the-art SiOx/HfO2 devices at the same EOT. Such performance enhancement can provide a strong advantage in the EOT-mobility trade-off which is commonly observed in scaled gate stacks, and has been linked by temperature and stress analyses to the higher physical thickness of the high-k interfacial layer, which results in attenuated remote phonon scattering compared to a SiOx interfacial layer achieving the same EOT.

Place, publisher, year, edition, pages
Stockholm: KTH Royal Institute of Technology, 2014. , xv, 107 p.
Series
TRITA-ICT/MAP AVH, ISSN 1653-7610 ; 2014:06
Keyword [en]
thulium, silicate, TmSiO, Tm2O3, interfacial layer, IL, CMOS, high-k, ALD
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Research subject
Information and Communication Technology
Identifiers
URN: urn:nbn:se:kth:diva-145116ISBN: 978-91-7595-115-7 (print)OAI: oai:DiVA.org:kth-145116DiVA: diva2:716192
Public defence
2014-05-27, Sal D, Forum, KTH, Isafjordsgatan 39, Kista, 10:00 (English)
Opponent
Supervisors
Note

QC 20140512

Available from: 2014-05-12 Created: 2014-05-08 Last updated: 2016-12-22Bibliographically approved
List of papers
1. In situ SiOx interfacial layer formation for scaled ALD high-k/metal gate stacks
Open this publication in new window or tab >>In situ SiOx interfacial layer formation for scaled ALD high-k/metal gate stacks
2012 (English)In: 2012 13th International Conference on Ultimate Integration on Silicon, ULIS 2012, IEEE , 2012, 105-108 p.Conference paper, Published paper (Refereed)
Abstract [en]

This work addresses the issue of interfacial layer formation in scaled high-k/metal gate stacks: the possibility of growing a thin SiOx interfacial layer in situ in a commercial ALD reactor has been evaluated, employing ozone-based Si oxidation. Three techniques (O3, O3/H2O and Pulsed) have been developed to grow scaled sub-nm interfacial layers and have been integrated in MOS capacitors and MOSFETs. A comparison based on electrical characterization shows that the performance of the proposed in situ methods is comparable or superior to that of existing ex situ techniques; specifically, the O3 method can grow aggressively scaled interfacial layers (4-5 A) while preserving the electrical quality of the stack.

Place, publisher, year, edition, pages
IEEE, 2012
Keyword
ALD, high-k, IL, ozone, SiOx
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-100024 (URN)10.1109/ULIS.2012.6193368 (DOI)2-s2.0-84861208486 (Scopus ID)978-146730191-6 (ISBN)
Conference
2012 13th International Conference on Ultimate Integration on Silicon, ULIS 2012; Grenoble; 6 March 2012 through 7 March 2012
Funder
EU, European Research Council
Note

QC 20120803

Available from: 2012-08-03 Created: 2012-08-03 Last updated: 2015-07-06Bibliographically approved
2. Characterization of thulium silicate interfacial layer for high-k/metal gate MOSFETs
Open this publication in new window or tab >>Characterization of thulium silicate interfacial layer for high-k/metal gate MOSFETs
2013 (English)In: 2013 14th International Conference On Ultimate Integration On Silicon (ULIS), IEEE , 2013, 122-125 p.Conference paper, Published paper (Refereed)
Abstract [en]

The possibility of integrating thulium silicate as IL (interfacial layer) in scaled high-klmetal gate stacks is explored. Electrical properties of the silicate IL are investigated in MOS capacitor structures for the silicate formation temperature range 500-900 degrees C. Results are compared to lanthanum silicate. A CMOS-compatible process flow for silicate formation is demonstrated, providing EOT of the IL as low as 0.1-0.3 nm and interface state density at flatband below 2.10(11) cm(-2)eV(-1). The silicate IL is found to be compatible with both gate-last and gate-first process flows, with a maximum thermal budget of 1000 degrees C.

Place, publisher, year, edition, pages
IEEE, 2013
Series
International Conference on Ultimate Integration on Silicon, ISSN 2330-5738
Keyword
TmSiO, LaSiO, silicate, interfacial layer, high-k
National Category
Engineering and Technology
Identifiers
urn:nbn:se:kth:diva-133499 (URN)10.1109/ULIS.2013.6523528 (DOI)000325214300030 ()2-s2.0-84880323601 (Scopus ID)978-1-4673-4802-7 (ISBN)
Conference
14th International Conference on Ultimate Integration on Silicon (ULIS), MAR 19-21, 2013, Coventry, England
Note

QC 20131106

Available from: 2013-11-06 Created: 2013-11-06 Last updated: 2014-05-12Bibliographically approved
3. High-Deposition-Rate Atomic Layer Deposition of Thulium Oxide from TmCp3 and H2O
Open this publication in new window or tab >>High-Deposition-Rate Atomic Layer Deposition of Thulium Oxide from TmCp3 and H2O
Show others...
2013 (English)In: Journal of the Electrochemical Society, ISSN 0013-4651, E-ISSN 1945-7111, Vol. 160, no 11, D538-D542 p.Article in journal (Refereed) Published
Abstract [en]

A novel process for atomic layer deposition of thulium oxide (Tm2O3) has been developed, employing TmCp3 as metal precursor and H2O as oxidizing agent. The use of a highly reactive oorganometallic precursor eliminates the need for a strong oxidizing agent (such as O-3) and provides a high deposition rate of similar to 1.5 angstrom/cycle. A thorough characterization of the process has been performed, identifying true ALD-type film growth in the temperature range 200-300 degrees C. The ALD process has been further investigated by extensive physical and electrical characterization of the deposited films in terms of-composition, crystalline phase, surface roughness and extraction of the dielectric constant. The films were found to be oxygen-rich Tm2O3, with low carbon impurity content at low deposition temperature and after annealing at 600 degrees C. The developed process produced polycrystalline films, with a surface roughness <1 nm RMS. Integration in MOS capacitors demonstrated well-behaved CV curves after annealing at 600 degrees C, with a relative dielectric constant of similar to 16.

Keyword
Chemical-Vapor-Deposition, Gate Dielectrics, Thin-Films, Precursors, Microelectronics, Kappa
National Category
Engineering and Technology
Identifiers
urn:nbn:se:kth:diva-138392 (URN)10.1149/2.056311jes (DOI)000326905000065 ()2-s2.0-84894800590 (Scopus ID)
Funder
EU, European Research Council, 228229 OSIRIS
Note

QC 20131220

Available from: 2013-12-20 Created: 2013-12-19 Last updated: 2017-12-06Bibliographically approved
4. Thulium silicate interfacial layer for scalable high-k/metal gate stacks
Open this publication in new window or tab >>Thulium silicate interfacial layer for scalable high-k/metal gate stacks
2013 (English)In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 60, no 10, 3271-3276 p.Article in journal (Refereed) Published
Abstract [en]

Interfacial layer (IL) control in high-k/metal gate stacks is crucial in achieving good interface quality, mobility, and reliability. A process is developed for the formation of a thulium silicate IL that can be integrated as a replacement for conventional chemical oxide ILs in gate-last high-k/metal gate CMOS process. A straightforward process integration scheme for thulium silicate IL is demonstrated, based on self-limiting silicate formation in inert gas atmosphere and with good selectivity of the etching step. The thulium silicate IL is shown to provide 0.25~{!@~}0.15 nm equivalent oxide thickness of the IL while preserving excellent electrical quality of the interface with Si. An interface state density ~0.7-21011 cm-2eV-1 was obtained at flat-band condition, and the nFET and pFET subthreshold slopes were 70 mV/dec. The inversion layer mobility was 20% higher than for the reference SiOx/HfO2 gate stack. Specifically, the measured mobility values were 230 cm2/ Vs for nFET and 60 cm2/Vs for pFET devices, at an inversion charge density of 1013 cm?2 and at a total capacitance equivalent thickness of 1.6 nm.

Keyword
High-k, interfacial layer (IL), scaled EOT, thulium, TmSiO
National Category
Engineering and Technology
Identifiers
urn:nbn:se:kth:diva-133169 (URN)10.1109/TED.2013.2275744 (DOI)000324928900040 ()2-s2.0-84884793585 (Scopus ID)
Funder
EU, European Research Council, 228229
Note

QC 20131029

Available from: 2013-10-29 Created: 2013-10-28 Last updated: 2017-12-06Bibliographically approved
5. Effective Workfunction Control in TmSiO/HfO2 high-k/metal gate stacks
Open this publication in new window or tab >>Effective Workfunction Control in TmSiO/HfO2 high-k/metal gate stacks
2014 (English)In: ULIS 2014: 2014 15th International Conference on Ultimate Integration on Silicon, 2014, 69-72 p.Conference paper, Published paper (Refereed)
Abstract [en]

Integration of high-k interfacial layers in CMOS technology has been proposed to overcome the scaling limitations of the SiOx/HfO2 dielectric stack. Candidate high-k interfacial layers have to be compatible with strict requirements in terms of EOT, inversion layer mobility, threshold voltage control and device reliability. We have previously demonstrated a CMOS-compatible process for integration of thulium silicate (TmSiO) as interfacial layer, providing advantages in terms of EOT and channel mobility. This work demonstrates the compatibility of the TmSiO/HfO2 stack with the threshold voltage control techniques commonly employed in gate-last and gate-first integration schemes, namely the use of a dual-metal process and the integration of dielectric capping layers. We show that the flatband voltage can be set from -1V to +0.5V by proper choice of gate metal, while a shift of 150-400 mV is achievable by means of integration of Al2O3 or La2O3 capping layers.

Series
International Conference on Ultimate Integration on Silicon, ISSN 2330-5738
Keyword
TmSiO, thulium, HfO2, CMOS, interfacial layer, high-k
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-153864 (URN)10.1109/ULIS.2014.6813908 (DOI)000341731300018 ()2-s2.0-84901302996 (Scopus ID)978-1-4799-3718-9 (ISBN)
Conference
15th International Conference on Ultimate Integration on Silicon (ULIS), APR 07-09, 2014, Stockholm, SWEDEN
Note

QC 20141009

Available from: 2014-10-09 Created: 2014-10-09 Last updated: 2016-12-22Bibliographically approved
6. Mobility enhancement by integration of TmSiO IL in 0.65nm EOT high-k/metal gate MOSFETs
Open this publication in new window or tab >>Mobility enhancement by integration of TmSiO IL in 0.65nm EOT high-k/metal gate MOSFETs
2013 (English)In: 2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC), IEEE Computer Society, 2013, 155-158 p.Conference paper, Published paper (Refereed)
Abstract [en]

Thulium silicate has been demonstrated as a possible replacement of chemical oxide interfacial layers for extended scalability of high-k/metal gate MOSFETs. In this work, thulium silicate was integrated in a scaled HfO 2/TiN gate-last CMOS process, achieving an EOT of 0.65 nm and well-behaved and reproducible IV and CV characteristics with almost symmetric threshold voltages, low subthreshold slope and low hysteresis. Comparison with reference devices employing chemical oxide interfacial layers shows improvement in terms of leakage current density and electron and hole mobility. Specifically, channel mobility is enhanced by 20% in N-MOSFETs and by 15% in P-MOSFETs at an inversion charge density of 1013cm-2, yielding values of 180 and 75 cm2/Vs at EOT = 0.65 and 0.8 nm respectively.

Place, publisher, year, edition, pages
IEEE Computer Society, 2013
Series
European Solid State Device Research Conference. Proceedings, ISSN 1930-8876
Keyword
CMOS integrated circuits, Hafnium oxides, Silicates, Thulium, C-V characteristic, Channel mobility, High-k/metal gates, Interfacial layer, Inversion charge density, Mobility enhancement, Reference devices, Subthreshold slope
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-145113 (URN)10.1109/ESSDERC.2013.6818842 (DOI)000342231600036 ()2-s2.0-84902181747 (Scopus ID)978-147990649-9 (ISBN)
Conference
43rd European Solid-State Device Research Conference, ESSDERC 2013; Bucharest; Romania; 16 September 2013 through 20 September 2013
Note

QC 20140911

Available from: 2014-05-08 Created: 2014-05-08 Last updated: 2014-10-27Bibliographically approved
7. Enhanced channel mobility by integration of sub-nm-EOT TmSiO/HfO2/TiNhigh-k/metal gate MOSFETs
Open this publication in new window or tab >>Enhanced channel mobility by integration of sub-nm-EOT TmSiO/HfO2/TiNhigh-k/metal gate MOSFETs
(English)Manuscript (preprint) (Other academic)
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-145145 (URN)
Note

QS 2014

Available from: 2014-05-12 Created: 2014-05-12 Last updated: 2014-05-12Bibliographically approved

Open Access in DiVA

Thesis(7529 kB)549 downloads
File information
File name FULLTEXT02.pdfFile size 7529 kBChecksum SHA-512
09b4378522d420f75b3c14da3cf44eaa00de7546069e2e03bcf2f0becbafecd6ddf905aa6a8c37510cbd7eebad7eda0c6f871bb24fbff7321be47aea7364cc8f
Type fulltextMimetype application/pdf

Search in DiVA

By author/editor
Dentoni Litta, Eugenio
By organisation
Integrated Devices and Circuits
Electrical Engineering, Electronic Engineering, Information Engineering

Search outside of DiVA

GoogleGoogle Scholar
Total: 717 downloads
The number of downloads is the sum of all downloads of full texts. It may include eg previous versions that are now no longer available

isbn
urn-nbn

Altmetric score

isbn
urn-nbn
Total: 558 hits
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf