Co-design of Fault-Tolerant Systems with Imperfect Fault Detection
Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
In recent decades, transient faults have become a critical issue in modernelectronic devices. Therefore, many fault-tolerant techniques have been proposedto increase system reliability, such as active redundancy, which can beimplemented in both space and time dimensions. The main challenge of activeredundancy is to introduce the minimal overhead of redundancy and to schedulethe tasks. In many pervious works, perfect fault detectors are assumed to simplifythe problem. However, the induced resource and time overheads of suchfault detectors make them impractical to be implemented. In order to tacklethe problem, an alternative approach was proposed based on imperfect faultdetectors.
So far, only software implementation is studied for the proposed imperfectfault detection approach. In this thesis, we take hardware-acceleration intoconsideration. Field-programmable gate array (FPGA) is used to accommodatetasks in hardware. In order to utilize the FPGA resources efficiently, themapping and the selection of fault detectors for each task replica have to be carefullydecided. In this work, we present two optimization approaches consideringtwo FPGA technologies, namely, statically reconfigurable FPGA and dynamicallyreconfigurable FPGA respectively. Both approaches are evaluated andcompared with the proposed software-only approach by extensive experiments.
Place, publisher, year, edition, pages
2014. , 38 p.
fault tolerant system
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:liu:diva-104942ISRN: LIU-IDA/LITH-EX-A--14/013--SEOAI: oai:DiVA.org:liu-104942DiVA: diva2:700239
Subject / course
Lifa, AdrianJiang, Ke