Biomedical electronics has gained significant attention in healthcare. A general biomedical device comprises energy source, analog-to-digital conversion (ADC), digital signal processing, and communication subsystem, each of which must be designed for minimum energy consumption to adhere to the stringent energy constraint.
The ADC is a key building block in the sensing stage of the implantable biomedical devices. To lower the overall power consumption and allow full integration of a complete biomedical sensor interface, it is desirable to integrate the entire analog front-end, back-end ADC and digital processor in a single chip. While digital circuits benefit substantially from the technology scaling, it is becoming more and more difficult to meet the stringent requirements on linearity, dynamic range, and power-efficiency at lower supply voltages in traditional ADC architectures. This has recently initiated extensive investigations to develop low-voltage, lowpower, high-resolution ADCs in nanometer CMOS technologies. Among different ADCs, the ΔΣ converter has shown to be most suitable for high-resolution and low-speed applications due to its high linearity feature.
This thesis investigates the design of high-resolution and power-efficient ΔΣ modulators at very low frequencies. In total, eight discrete-time (DT) modulators have been designed in a 65nm CMOS technology: two active modulators, two hybrid active-passive modulators, two ultra-low-voltage modulators operated at 270mV and 0.5V supply voltages, one fully passive modulator, and a dual-mode ΔΣ modulator using variable-bandwidth amplifiers.
The two active modulators utilize traditional feedback architecture. The first design presents a simple and robust low-power second-order ΔΣ modulator for accurate data conversion in implantable rhythm management devices such as cardiac pacemakers. Significant power reduction is achieved by utilizing a two-stage load-compensated OTA as well as the low-Vth devices in analog circuits and switches. An 80dB SNR (13-bit) was achieved at the cost of 2.1μW power in 0.033mm2 chip core area. The second design introduces a third-order modulator adopting the switched-opamp and partially body-driven gain-enhanced techniques in the OTAs for low-voltage and low-power consumption. The modulator achieves 87dB SNDR over 500Hz signal bandwidth, consuming 0.6μW at 0.7V supply.
The two hybrid modulators were designed using combined SC active and passive integrators to partially eliminate the analog power associated with the active blocks. The first design employs an active integrator in the 1st stage and a passive integrator in the less critical 2nd stage. A 73.5dB SNR (12-bit) was achieved at the cost of 1.27μW power in a 0.059mm2 chip core area. The latter modulator utilizes a fourth-order active-passive loop filter with only one active stage. The input-feedforward architecture is used to improve the voltage swing prior to the comparator of the traditional passive modulators, which enables a simpler comparator design without requiring a preamplifier. It also allows the use of three successive passive filters to obtain a higher-order noise shaping. The modulator attains 84dB SNR while dissipating 0.4μW power at a 0.7V supply.
Two ultra-low-voltage DT modulators operating at 0.5V and the state-of-the-art 270mV power supplies were proposed. The former modulator employs fully passive loop filter followed by a 0.5V preamplifier and dynamic comparator, whereas the latter one exploits the inverter-based integrators combined with clock boosting scheme for adequate switches overdrive voltage. The first design incorporates a gain-boosted scheme using charge redistribution amplification in the passive filter as well as a body-driven gain-enhanced preamplifier prior to the comparator in order to compensate for the gain shortage. It attains 75dB SNR consuming 250nW power, which is a record amongst the state-of-the-art ultra-lowpower ΔΣ modulators. The second design uses feedforward architecture that suggests low integrators swing, enabling ultra-low-voltage operation. The degraded gain, GBW and SR of the inverter amplifiers operating at such a low voltage are enhanced by a simple current-mirror output stage. The attained FOM is 0.31pJ/step.
A fully passive DT modulator was presented aiming for analog power reduction, the dominant part of the power in the active modulators. A careful analysis of the non-idealities in the passive filter, including the noise, parasitic effect, and integrator’s leakage were essential to meet the performance requirement necessary for an implantable device. The chip was tested simultaneously with its active counterpart, showing significant power reduction at the cost of 4× core area and 12dB SNR loss.
The designed dual-mode modulator employs variable-bandwidth amplifiers in combination with oversampling ratio to provide tunable resolution. This work presents the design, implementation, and test results of a two-stage amplifier using the second stage replica, that provides tunable GBW with consistent DC gain.
Linköping: Linköping University Electronic Press, 2014. , 124 p.
2014-01-21, Visionen, B-huset, Campus Valla, Linköpings universitet, Linköping, 13:15 (English)
Anderson, Martin, Dr.