Hardware Architecture for Real-time Computation of Image Component Feature Descriptors on a FPGA
2014 (English)In: International Journal of Distributed Sensor Networks, ISSN 1550-1329, E-ISSN 1550-1477, Art. no. 815378- p.Article in journal (Refereed) Published
This paper describes a hardwarearchitecture for real-time image component labelingand the computation of image component featuredescriptors. These descriptors are object relatedproperties used to describe each image component.Embedded machine vision systems demand a robustperformance, power efficiency as well as minimumarea utilization, depending on the deployedapplication. In the proposed architecture, the hardwaremodules for component labeling and featurecalculation run in parallel. A CMOS image sensor(MT9V032), operating at a maximum clock frequencyof 27MHz, was used to capture the images. Thearchitecture was synthesized and implemented on aXilinx Spartan-6 FPGA. The developed architecture iscapable of processing 390 video frames per second ofsize 640x480 pixels. Dynamic power consumption is13mW at 86 frames per second.
Place, publisher, year, edition, pages
2014. Art. no. 815378- p.
Electrical Engineering, Electronic Engineering, Information Engineering Embedded Systems
IdentifiersURN: urn:nbn:se:miun:diva-20382DOI: 10.1155/2014/815378ISI: 000330042300001ScopusID: 2-s2.0-84893832573Local ID: STCOAI: oai:DiVA.org:miun-20382DiVA: diva2:668162