Lossless video compression in an FPGA for reducing DDR memory bandwidth usage
We show that a hardware implementation of a lossless image compression scheme
can be used as means for lowering DDR memory bandwidth usage from a video
stream. A prediction scheme based on LOCO-I is used to reduce correlative redundancy
between sequential pixels, before the data is encoded by Golomb coding.
The data packages after source coding contain a continuous stream of prefix codes,
in order to eliminate the header data imposed by more advanced packing schemes.
This in turn results in a higher demand on the decoding side in terms of resource
usage, because of the need for high parallelism when a new prefix code is counted
and decoded each clock cycle.
The test images are reduced in size by 49-84%, depending on their inherent complexity.
Resource consumption for this design amounts to 10100 Logic Elements
(synthesized for an Altera Cyclon III FPGA - EP3C80F484C6), with a operating
frequency of 152,86 MHz for a throughput of 458 MB/s. These numbers can be
improved by reducing the algorithm complexities. LE usage is reduced to 4695,
while accomplishing a image size reduction of 34-59%.
We present a way to increase decompression throughput by adding parallel decoder
modules. Those changes will increase throughput to a multiple of 458 MB/s while
worsening the compression somewhat. LE cost increases depending on the level of
Place, publisher, year, edition, pages
Institutt for elektronikk og telekommunikasjon , 2013. , 192 p.
IdentifiersURN: urn:nbn:no:ntnu:diva-22734Local ID: ntnudaim:9571OAI: oai:DiVA.org:ntnu-22734DiVA: diva2:651974
Svarstad, Kjetil, ProfessorLinnerud, Jørgen