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Estimating the Energy Consumption of Emerging Random Access Memory Technologies
Norwegian University of Science and Technology, Faculty of Information Technology, Mathematics and Electrical Engineering, Department of Electronics and Telecommunications.
2013 (English)MasteroppgaveStudent thesis
Abstract [en]

In this work, a model for estimating the energy consumption of different types of random access memory(RAM) technologies, likely to be commercially available by 2017, has been developed. The goal for this model has been to evaluate which of the memory technologies that will be the most energy efficient in 2017. This was done by building the model on the required energies to read or write a bit for the different technologies. The memory technologies that have been modelled are: Dynamic RAM (DRAM), Static RAM (SRAM), Ferroelectric RAM (FeRAM), Magnetic RAM (MRAM), Spin-Torque Transfer Magnetic RAM (STT-MRAM) and Phase Change RAM (PCRAM). The volatile memory technologies, DRAM and SRAM, have been estimated to have the lowest energy consumption if the memories are operated at a high duty cycle. However, if the duty cycle is reduced, the emerging non-volatile memory technologies become more energy efficient. The FeRAM was estimated to have the lowest power consumption when manufactured with the technology available today. And it has been estimated that with a duty cycle lower than 8.5 × E−4, FeRAM technology consumes less power than the SRAM, and with a duty cycle lower than 1.6 × E−4, the FeRAM consumes less power than DRAM. When looking forward towards 2017, STT-MRAM was estimated to have the lowest power consumption of the emerging memory technologies. It was estimated that the STT-MRAM consumes less power than SRAM for duty cycles lower than 2.3 × E−2 and consumes less power than the DRAM for duty cycles lower than 4.6 × E−4. An experimental set-up has been developed to validate the model, and a case study of some selected memories has been performed. With this case study some limitations on the theoretical model have been pointed out. These limitations are believed to be reduced if the memories are embedded on chip.

Place, publisher, year, edition, pages
Institutt for elektronikk og telekommunikasjon , 2013. , 257 p.
URN: urn:nbn:no:ntnu:diva-22566Local ID: ntnudaim:9897OAI: diva2:649811
Available from: 2013-09-19 Created: 2013-09-19 Last updated: 2013-09-19Bibliographically approved

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