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KTH, School of Information and Communication Technology (ICT).
2013 (English)Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
Abstract [en]

MPSoCs serve for the needs of the modern embedded systems by providing computationally powerful and flexible platforms. However, due to the design productivity gap and some architectural and methodological challenges, the successful design of real-time applications on these platforms is becoming a pressing concern. Methodologies starting with models at low levels of abstractions often are limited in their design space exploration. One way to improve the situation is by introducing formally analyzable models and entering the design process at a high level of abstraction. This approach enables the creation of correct-by-construction designs. ForSyDe is a modeling framework for embedded systems based on the theory of formal models of computation and it allows specification of systems at a high abstraction level. On the other hand, architectural challenges such as unpredictable timing behavior and interference between applications call for predictable and composable architectures. The CompSOC platform has a predictable and composable architecture and its design flow can map analyzable data-flow applications to an MPSoC in a way that guarantees the real-time requirements of the applications. Methodological challenges such as the automation of the design flows and tool interoperability are other major contributers of the design productivity gap, hence these aspects of a design flow are of paramount importance. By combining the ForSyDe and the CompSOC design flows, this thesis proposes a design flow that starts with a high level model of the system. By formal analysis, this design flow can produce a mapping of application tasks to an MPSoC platform. The design flow can implement an FPGA prototype of the system. The design flow is automated and as case studies, two image processing applications are implemented. These two applications are used to validate the design flow.

Place, publisher, year, edition, pages
2013. , 138 p.
Trita-ICT-EX, 2013:137
National Category
Engineering and Technology
URN: urn:nbn:se:kth:diva-128519OAI: diva2:647797
Educational program
Master of Science - System-on-Chip Design
Available from: 2013-09-12 Created: 2013-09-12 Last updated: 2013-09-12Bibliographically approved

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