As the age of Moore’s law is drawing to a close, continuing increase in computing performance is becoming increasingly hard‐earned, while demand for bandwidth is insatiable. One way of dealing with this challenge is the integration of active photonic material with Si, allowing high‐speed optical inter‐ and intra‐chip connects on one hand, and the economies of scale of the CMOS industry in optical communications on the other. One of the most essential active photonic materials is InP, stemming from its capability in combination with its related materials to produce lasers, emitting at wavelengths of 1300 and 1550 nm, the two most important wavelengths in data‐ and telecom.
However, integrating InP with Si remains a challenging subject. Defects arise due to differences in lattice constants, differences in thermal expansion coefficients, polarity and island‐like growth behavior. Approaches to counter these problems include epitaxial lateral overgrowth (ELOG), which involves growing InP laterally from openings in a mask deposited on a defective InP/Si substrate. This approach solves some of these problems by filtering out the previously mentioned defects. However, filtering may not be complete and the ELOG and mask themselves may introduce new sources for formation of defects such as dislocations and stacking faults.
In this work, the various kinds of defects present in InP ELOG layers grown by hydride vapor phase epitaxy on Si, and the reason for their presence, as well as strategies for counteracting them, are investigated. The findings reveal that whereas dislocations appear in coalesced ELOG layers both on InP and InP/Si, albeit to varying extents, uncoalesced ELOG layers on both substrate types are completely free of threading dislocations. Thus, coalescence is a critical aspect in the formation of dislocations. It is shown that a rough surface of the InP/Si substrate is detrimental to defect‐free coalescence. Chemical‐mechanical polishing of this surface improves the coalescence in subsequent ELOG leading to fewer defects.
Furthermore, ELOG on InP substrate is consistently free of stacking faults. This is not the case for ELOG on InP/Si, where stacking faults are to some extent propagating from the defective substrate, and are possibly also forming during ELOG. A model describing the conditions for their propagation is devised; it shows that under certain conditions, a mask height to opening width aspect ratio of 3.9 should result in their complete blocking. As to the potential formation of new stacking faults, the formation mechanism is not entirely clear, but neither coalescence nor random deposition errors on low energy facets are the main reasons for their formation. It is hypothesized that the stacking faults can be removed by thermal annealing of the seed and ELOG layers.
Furthermore, concepts for integrating an active photonic device with passive Si components are elucidated by combining Si/SiO2 waveguides used as the mask in ELOG and multi‐quantum well (MQW) lasers grown on ELOG InP. Such a device is found to have favorable thermal dissipation, which is an added advantage in an integrated photonic CMOS device.
Stockholm: KTH Royal Institute of Technology, 2013. , 85 p.
2013-09-27, Sal/Hall E, Forum, KTH-ITC, Isafjordsgatan 39, Kista, 10:00 (English)