Efficiency Enhancement Techniques for a 0.13 µm CMOS DECT PA
Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
Different efficiency enhancement techniques for a 1.9 GHz DECT power amplifier (PA) have been investigated. Generally, a higher efficiency can be achieved by varying the supply voltage and/or the bias of the PA or by making topology and/or class changes. In this work, changes in bias and topology have been studied. Focus has been on enhancing efficiency at power back-off to increase talk-time for handset applications. The PA used in this study was a two stage 0.13 μm CMOS PA for 2.5 V operation. In its original
configuration, it delivered 28.3 dBm of maximum output power with a PAE of 43.5 % (simulated). At 10 dB power back-off the PAE was only 15.9 %. The largest improvement was obtained using a topology change with the amplifying transistor split into two parallel transistors (class A and B) with variable bias. The PA delivered 29.1 dBm to the load with a PAE of 45.1 %, and 18 % PAE at power back-off; a relative improvement at this level with 13 %. The new PA topology does not require any additional area.
Place, publisher, year, edition, pages
2007. , 58 p.
Engineering and Technology
IdentifiersURN: urn:nbn:se:liu:diva-96235ISRN: LITH-ITN-ED-EX--07/009--SEOAI: oai:DiVA.org:liu-96235DiVA: diva2:644766
Subject / course