Two-step continuous-time incremental sigma-delta ADC
2013 (English)In: Electronics Letters, ISSN 0013-5194, E-ISSN 1350-911X, Vol. 49, no 12, 749-750 p.Article in journal (Refereed) Published
A two-step continuous-time (CT) incremental sigma-delta (I Sigma Delta) ADC, which enhances the performance of conventional CT I Sigma Delta ADCs, is proposed. By pipelining two second-order CT I Sigma Delta ADCs, the proposed two-step architecture can achieve high resolution without sacrificing the conversion rate. Compared to other alternatives, the two-step CT I Sigma Delta ADC exhibits the freedom of adjusting its accuracy and speed independently while featuring quite relaxed circuit specifications.
Place, publisher, year, edition, pages
IEEE Press, 2013. Vol. 49, no 12, 749-750 p.
Circuit specifications, Continuoustime, Conversion rates, High resolution, Second orders, Sigma-delta, Sigma-delta ADC
Electrical Engineering, Electronic Engineering, Information Engineering
Research subject SRA - ICT
IdentifiersURN: urn:nbn:se:kth:diva-124547DOI: 10.1049/el.2013.1096ISI: 000321716500014ScopusID: 2-s2.0-84879761031OAI: oai:DiVA.org:kth-124547DiVA: diva2:636299
FunderSwedish Research Council
QC 201307102013-07-092013-07-092013-08-16Bibliographically approved