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Design of a Rom-Less Direct Digital Frequency Synthesizer in 65nm CMOS Technology
Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
2013 (English)Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
Abstract [en]

A 4 bit, Rom-Less Direct Digital Frequency Synthesizer (DDFS) is designed in 65nm CMOS technology. Interleaving with Return-to-Zero (RTZ) technique is used to increase the output bandwidth and synthesized frequencies. The performance of the designed synthesizer is evaluated using Cadence Virtuoso design tool. With 3.2 GHz sampling frequency, the DDFS achieves the spurious-free dynamic range (SFDR) of 60 dB to 58 dB for synthesized frequencies between 200 MHz to 1.6 GHz. With 6.4 GHz sampling frequency, the synthesizer achieves the SFDR of 46 dB to 40 dB for synthesized frequencies between 400 MHz to 3.2 GHz. The power consumption is 80 mW for the designed mixed-signal blocks.

Place, publisher, year, edition, pages
2013. , 68 p.
Keyword [en]
Rom-Less DDFS, Current Steering Digital-to-Analog Converter, Interleaved DACs, Return-to-Zero, Sine weighted DAC
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:liu:diva-91680ISRN: LiTH-ISY-EX--13/4657--SEOAI: oai:DiVA.org:liu-91680DiVA: diva2:618514
Subject / course
Electronic Devices
Presentation
2013-04-16, Linköping, 14:03 (English)
Uppsok
Technology
Supervisors
Examiners
Available from: 2013-04-29 Created: 2013-04-29 Last updated: 2013-04-29Bibliographically approved

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CiteExportLink to record
Permanent link

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Citation style
  • apa
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Output format
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