En variabel bit lengde 9-bit 50MS/S SAR ADC
2012 (Bokmål, Norwegian; Norwegian Bokmål)
MasteroppgaveStudent thesisAlternative title
A Variable Bit Length 9-bit 50MS/s SAR ADC (English)
A 9-bit 50MS/s SAR ADC with a simulated power consumption of 24.5 µW was designed for this thesis. Speciﬁcations were made for application with in-probe electronic as part of an ultrasound system. A novel switching-scheme - employing variable bit length encoding – was introduced in order to simplify successive approximation. Pre-layout results reported a FoM of just 1.37 fJ/conversion step, which is favorable to all published designs to date. Recent technology advancements has seen the ultrasound ﬁeld expanding into handheld markets . More power eﬃcient solutions, in addition to existing enhanced resolution 3-D technology both place strict requirements for analog/mixed-signal design. Composite electronics within the probe casing - allowing close-to-source signal processing - is believed to be the future of ultrasound devices. ADC designs suitable for in-probe technology require ultra low power and noise characteristics towards supporting multiple channels on a single SoC. Excellent performance of recent SAR ADCs make them a viable alternative for in-probe technology [2,7,12,4]. Work in this thesis show the ﬂexibility of the SAR algorithm. The relatively simple implementation/decoding of the VBL approach, complimented by the accuracy dependency of the level detection range makes the ADC reconﬁgurable by digital signal processing. Recent published design has reported relatively low power consumption for the comparator [15,7]. A motivation for the thesis was to see whether multiple operated comparators could reduce power in remaining circuitry. Implementation of a level-detector - supporting the VBL switching-scheme - has lead to improvements in: Power eﬃciency, speed and metastability-induced errors. The device consists of two comparators operated in parallel, with a relative DC-oﬀset generated by diﬀerence in the capacitive load. Decision points of the comparators shift with DC-oﬀset, and are atoned for a range desired by the modiﬁed SAR algorithm. An extensive literary search of recent methodologies and results was conducted, and a summery presenting state-of-the-art designs is included with the work. An approach using no external references where chosen as a basis for the DAC design. Emphasize was made on constant common-mode voltage suitably for comparator design eliminating pre-ampliﬁers or buﬀers. Digital logic consisting of serial connected bitslices using a novel diﬀerential approach is proposed. Level detector outputs are connected to the digital logic switching only a portion of transistors in the bitslice during conversion. Trade-oﬀ between switching activity and circuit area proves eﬀective, with only 12.5% of overall power consumed in the digital part. Power simulations reported the level-detector as the dominant source of consumption, thereby being subject to further optimization with regards to power. Nonetheless a proof-of-concept 8-bit ADC implementation - operated with the novel switching-scheme - produced 8.96 ENOB while dissipating less power.
Place, publisher, year, edition, pages
Institutt for elektronikk og telekommunikasjon , 2012. , 124 p.
IdentifiersURN: urn:nbn:no:ntnu:diva-20654Local ID: ntnudaim:8501OAI: oai:DiVA.org:ntnu-20654DiVA: diva2:616113
Ytterdal, Trond, Professor