Emerging macro- and flexible electronic applications such as foldable displays, artificial skins, and smart textiles grow rapidly into the market. Solution-processed thin-film transistors (TFTs) based on single-walled carbon nanotubes (SWCNTs) as the semiconductor channel can offer high performance, low cost and versatility for macro- and flexible electronics. Major challenges to the development of SWCNT-based TFTs include: (i) hysteresis in their transfer characteristics (TCs), (ii) difficulties in simultaneous achievements of high on-state current Ion and large on/off current ratio Ion/Ioff, and (iii) poor uniformity and scalability resulting from the poor solution processability. This thesis aims at developing reliable and simple process techniques for fabrication of the SWCNT-based TFTs that possess the afore-stated characteristics. It presents a systematic investigation to not only explore the fundamental device physics, but also develop novel fabrication methods for enhancement of device performance.
First, issues related to the measurement of gate capacitance (Cg), the determination of current scalability, and the hysteresis in randomly networked SWCNTs are properly addressed. This leads to the establishment of a comprehensive methodology for extraction of carrier mobility (μ) for the SWCNT-based TFTs. In detail, the large hysteresis is effectively suppressed by adopting a pulsed drain current-gate voltage (Id-Vg) method in which the polarity of the gate pulse was alternating during the measurement. Different from most reported methods in the literature, Cg is accurately determined in our case by performing direct capacitance-voltage measurement on the TFTs.
Second, with the employment of functional composites comprising SWCNTs embedded in a semiconducting polymer, poly-9,9 dioctyl-fluorene-cobithiophene (F8T2), as the semiconducting channel via facile solution processes under ambient conditions, the fabricated TFTs exhibit outstanding electrical performance with: (i) negligible hysteresis, (ii) high μ, (iii) high Ion and large Ion/Ioff, (iv) excellent uniformity and dimensional scalability, and (v) good stability. These highly desired performance parameters are achieved owing to an ideal composite structure with metallic SWCNTs being selectively removed and the remaining semiconducting SWCNTs being well wrapped by the polymer matrix.
Finally, the developed TFTs basing on the SWCNT/F8T2 composite are used as the building block to construct some logic circuits. The resultant inverters, NANDs, and NORs are found to retain the small-hysteresis characteristics, with a cut-off frequency reaching 100 kHz. The results presented in this thesis advance the state-of-art SWCNT-based macroelectronics.
Uppsala: Acta Universitatis Upsaliensis, 2013. , 62 p.
2013-05-30, Häggsalen, Ångström Laboratory, Lägerhyddsvägen 1, Uppsala, 13:15 (English)