Change search
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf
FPGA Implementation of Flexible Interpolators and Decimators
Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
2013 (English)Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
Abstract [en]

The aim of this thesis is to implement flexible interpolators and decimators onField Programmable Gate Array (FPGA). Interpolators and decimators of differentwordlengths (WL) are implemented in VHDL. The Farrow structure is usedfor the realization of the polyphase components of the interpolation/decimationfilters. A fixed set of subfilters and adjustable fractional-delay multiplier valuesof the Farrow structure give different linear-phase finite-length impulse response(FIR) lowpass filters. An FIR filter is designed in such a way that it can be implementedfor different wordlengths (8-bit, 12-bit, 16-bit). Fixed-point representationis used for representing the fractional-delay multiplier values in the Farrow structure. To perform the fixed-point operations in VHDL, a package called fixed pointpackage [1] is used.

A 8-bit, 12-bit, and 16-bit interpolator are implemented and their performancesare verified. The designs are compiled in Quartus-II CAD tool for timing analysisand for logical registers usage. The designs are synthesised by selecting Cyclone IVGX family and EP4X30CF23C6 device. The wordlength issues while implementingthe interpolators and decimators are discussed. Truncation of bits is required inorder to reduce the output wordlength of the interpolator and decimator.

Place, publisher, year, edition, pages
2013. , 70 p.
Keyword [en]
Interpolation, Decimation, Linear-phase FIR interpolation, VHDL implementation of interpolators and decimators
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:liu:diva-89761ISRN: LiTH-ISY-EX--13/4654--SEOAI: oai:DiVA.org:liu-89761DiVA: diva2:609369
Subject / course
Master of Science in Electronics Design Engineering
Presentation
2013-02-21, Nollstället, Linköping University, Linköping, 13:15 (English)
Uppsok
Technology
Supervisors
Examiners
Available from: 2013-03-06 Created: 2013-03-05 Last updated: 2013-03-06Bibliographically approved

Open Access in DiVA

FPGA Implementation of Flexible Interpolators and Decimators(1707 kB)4662 downloads
File information
File name FULLTEXT01.pdfFile size 1707 kBChecksum SHA-512
16abeb03c901e48d9d335350948964e286b8ddb653d95b759096f7acf5396a6028a9c1f5e44961e4ddcbcdacbaf1c571da8d43a409407b619d417f22abb3c893
Type fulltextMimetype application/pdf

Search in DiVA

By author/editor
VenkataVikram, Dabbugottu
By organisation
Electronics SystemThe Institute of Technology
Electrical Engineering, Electronic Engineering, Information Engineering

Search outside of DiVA

GoogleGoogle Scholar
Total: 4662 downloads
The number of downloads is the sum of all downloads of full texts. It may include eg previous versions that are now no longer available

urn-nbn

Altmetric score

urn-nbn
Total: 812 hits
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf