Pipelined Radix-2(k) Feedforward FFT Architectures
2013 (English)In: IEEE Transactions on Very Large Scale Integration (vlsi) Systems, ISSN 1063-8210, Vol. 21, no 1, 23-32 p.Article in journal (Refereed) Published
The appearance of radix-2(2) was a milestone in the design of pipelined FFT hardware architectures. Later, radix-2(2) was extended to radix-2(k). However, radix-2(k) was only proposed for single-path delay feedback (SDF) architectures, but not for feedforward ones, also called multi-path delay commutator (MDC). This paper presents the radix-2(k) feedforward (MDC) FFT architectures. In feedforward architectures radix-2(k) canbe used for any number of parallel samples which is a power of two. Furthermore, both decimation in frequency (DIF) and decimation in time (DIT) decompositions can be used. In addition to this, the designs can achieve very high throughputs, which makes them suitable for the most demanding applications. Indeed, the proposed radix-2(k) feedforward architectures require fewer hardware resources than parallel feedback ones, also called multi-path delay feedback (MDF), when several samples in parallel must be processed. As a result, the proposed radix-2(k) feedforward architectures not only offer an attractive solution for current applications, but also open up a new research line on feedforward structures.
Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE) , 2013. Vol. 21, no 1, 23-32 p.
Fast Fourier transform (FFT), multipath delay commutator (MDC), pipelined architecture, radix-2(k), VLSI
Engineering and Technology
IdentifiersURN: urn:nbn:se:liu:diva-88360DOI: 10.1109/TVLSI.2011.2178275ISI: 000312835000003OAI: oai:DiVA.org:liu-88360DiVA: diva2:602884
Funding Agencies|FPU Fellowship of Spanish Ministry of Education|AP2005-0544|Spanish National Research and Development Program|TEC2008-02148|Swedish ELLIIT Program||2013-02-042013-02-042015-03-11