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A Study of Output Impedance Effects in Current-Steering Digital-to-Analog Converters
Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology. (Electronics Systems)
Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology. (Electronics Systems)
2013 (English)Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
Abstract [en]

In this thesis, we have explained the different types of DAC (Digital-to-Analog) architectures and their advantages and disadvantages. We have mainly focused on current-steering digital-to-analog design for achieving high speed and high performance. The current-steering DAC is designed using binary weighted architecture. The benefits of this architecture is that it occupies less area, consumes less power and the number of control signals required are very less.

The requirements for high speed and high performance DAC are discussed in detail. The circuit is implemented in a state-of-the-art 65 nm process, with a supply voltage of 1.2 V and at a sampling speed of 2 GHz. The resolution of the DAC is 8-bits. The design of 8-bit current-steering DAC converts 8 most significant bits (MSBs) into their binary weighted equivalent, which controls 256 unit current sources.

The performance of the DAC is measured using the static and dynamic  parameters. In communication applications the static performance measures such as INL and DNL are not of utmost importance. In this work, we have mainly concentrated on the dynamic performance characteristics like SNR (Signal to Noise Ratio) and SFDR (Spurious Free Dynamic Range). For measuring the dynamic parameters, frequency domain analysis is a better choice.

Also, we have discussed how the pole-zero analysis can be used to arrive at the dynamic performance metrics of a unit element of the DAC at higher frequencies. Different methods were discussed here to show the effects of poles and zeroes on the output impedance of a unit element at higher frequencies, for example, by hand calculation, using Mathematica and by using cadence.

After extensive literature studies, we have implemented a technique in cadence, to increase the output impedance at higher frequencies. This technique is called as “complimentary current solution technique”. This technique will improve the output impedance and SFDR compared to the normal unit element design.

Our technique contains mostly analog building blocks, like, current mirrors, biasing scheme and switching scheme and few digital blocks like D-ff (D-flip flop). The whole system is simulated and verified in MATLAB. Dynamic performances of the DAC such as SNR and SFDR are found with the help of MATLAB.

Place, publisher, year, edition, pages
2013. , 116 p.
Keyword [en]
Unit element, Current mirror, pole-zero analysis of unit-element, SFDR
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:liu:diva-87399ISRN: LiTH-ISY-EX--13/4576--SEOAI: oai:DiVA.org:liu-87399DiVA: diva2:589289
Subject / course
Electronics Systems
Presentation
2012-06-12, Nollstället, Electronics Systems Linköpings universitet 581 83 LINKÖPING, Linkoping, 09:00 (English)
Uppsok
Technology
Supervisors
Examiners
Available from: 2013-01-30 Created: 2013-01-17 Last updated: 2013-01-30Bibliographically approved

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