Analysis of Exponentially Decaying Pulse Shape DACs in Continuous-Time Sigma-Delta Modulators
2012 (English)In: Electronics, Circuits and Systems (ICECS), 2012 19th IEEE International Conference on, IEEE , 2012, 424-427 p.Conference paper (Refereed)
The performance of continuous-time (CT) sigma-delta (ΣΔ) modulators is severely degraded by the clock jitter induced timing variation in their feedback digital-to-analog converters (DACs). To mitigate this non-ideality, jitter sensitivity reduction techniques that employ exponentially decaying pulse shape DACs have been recently reported. In this paper, exponentially decaying DACs are investigated and generalized expressions are derived. In addition, another exponentially decaying DAC proposed, which can potentially achieve both good jitter immunity and amplitude efficiency. To validate the theoretical results, the proposed DAC, together with other exponentially decaying DACs, are employed in a 3rd order 1-bit CT ΣΔ modulator test case and evaluated through behavioral simulations.
Place, publisher, year, edition, pages
IEEE , 2012. 424-427 p.
Behavioral simulation, Clock-jitter, Continuous-time sigma-delta modulators, Continuoustime, Digital-to-analog converters, Nonideality, Pulse shapes, Sensitivity reduction technique, Sigma-delta, Test case, Theoretical result, Timing variations
Electrical Engineering, Electronic Engineering, Information Engineering
Research subject SRA - ICT
IdentifiersURN: urn:nbn:se:kth:diva-109729DOI: 10.1109/ICECS.2012.6463659ScopusID: 2-s2.0-84874601068ISBN: 978-146731261-5OAI: oai:DiVA.org:kth-109729DiVA: diva2:583740
IEEE International Conference on Electronics, Circuits, and Systems (ICECS), Seville, Spain, 9-12 December, 2012
FunderSwedish Research Council
QC 201301082013-01-082013-01-082013-04-03Bibliographically approved