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IGCT Transient Analysis and Clamp Circuit Design for VSC valves
KTH, School of Electrical Engineering (EES), Electrical Energy Conversion.
2012 (English)Independent thesis Advanced level (professional degree), 20 credits / 30 HE creditsStudent thesis
Abstract [en]

In today’s high power VSCs (Voltage Source Converters), IGBTs (Insulated Gate Bipolar Transistors) are the dominant semiconductors. These converters are in general modular multilevel based and contain several building blocks that are series connected. Each of these building blocks in turn consist of several series connected IGBT valves. One of the advantages of using modular multilevel based VSCs is the ability to switch each building block at a lower frequency compared to the average total switching frequency of the converter. IGBTs generally have lower switching losses than other semiconductors, however, their on-state losses are higher because of a larger on-state voltage. Furthermore, series connection of IGBTs devices imposes voltage sharing complications that are generally difficult to deal with. A solution to this problem is to increase the amount of series connected building blocks and thus avoid series connection of semiconductors. To lower the semiconductor on-state losses, either the IGBTs are replaced by improved IGBT and drives or an alternative semiconductor that is more suited for modular multilevel topologies can be used. In this thesis, an alternative semiconductor called IGCT (Integrated Gate-Commutated Thyristor) is studied; more specifically RC-IGCT (Reverse Conducting IGCT). An analytic analysis is conducted to grasp the switching behavior, furthermore, a simulation model in PspiceR is proposed for confirming the analytic analysis. This model is also used for parameter sweeps of clamp circuit components from which a table is created. This table can be used for comprehending the effects of changing values on the switching transient and also for the design of clamp circuit components. However, a numerical and a graphical method together with the PspiceR model are proposed for designing the clamp circuit. It is found that the graphical method is far more intuitive and revealing than the numerical. If further accuracy is required, then the graphical method can be used in tandem with the numerical. A fault case analysis of the clamp circuit is conducted in order to reveal how failures in the clamp components affect the semiconductors and other components in a building block. Some of these failures are more destructive than others. The IGCT building block states and current paths are discussed and finally series connection of IGCTs is considered.

Place, publisher, year, edition, pages
2012. , 77 p.
EES Examensarbete / Master Thesis, XR-EE-E2C 2012:014
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
URN: urn:nbn:se:kth:diva-109650OAI: diva2:583522
Educational program
Master of Science in Engineering - Electrical Engineering
Available from: 2013-01-31 Created: 2013-01-08 Last updated: 2013-01-31Bibliographically approved

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