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Extended Junction Based Source Routing Technique for Large Mesh Topology Network on Chip Platforms
Jönköping University, School of Engineering, JTH, Computer and Electrical Engineering.
2011 (English)Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
Abstract [en]

Network on Chip (NoC) has been proposed as a scalable and flexible interconnect infrastructure for communication among hundreds of cores on a core-based System on Chip. Routing algorithm affects the communication performance of a NoC. Therefore, many researchers have proposed different routing techniques in their work. Source routing, with many advantages over distributed routing, is very suitable for NoC platforms but has a serious drawback of overhead for storing the path information in every packet header. A technique called Junction Based Routing (JBR) was proposed to overcome this limitation of source routing. In JBR, either the packet reaches the destination directly, or reaches a junction from where it picks up the path information for on-ward path towards the destination. However, JBR has few drawbacks such as increased packet latency due to the delay involved in fetching the new path information from junction nodes, increased path length overhead using minimum number of junctions and deadlocks while even using the deadlock free routing algorithms.

 

In this thesis we proposed a technique, called Extended Junction Based Routing (EJBR), to address the limitations of JBR. EJBR reduces the packet latency for the communicating pairs of nodes involving multiple junctions. We are using three virtual channels to avoid deadlocks and to make communication from junction to junction faster we are reducing the delay at intermediate routers among them by skipping routers pipeline stages. There are many interesting issues related to this approach. We discuss and solve three important issues related to EJBR, namely, number and position of junctions, junctions network topology and path computation for efficient deadlock free routing. A simulator has been developed to evaluate the performance of EJBR with simple source routing and JBR. We also developed a tool in MATLAB to find the efficient junctions network topology and to compute the paths for deadlock free routing. The results of simulations show that the performance of EJBR is better than JBR for few routing algorithms in terms of latency and throughput. 

Place, publisher, year, edition, pages
2011. , 90 p.
Keyword [en]
Networks on Chip (NoC), System on Chip (SoC), Routing Algorithms, Source Routing, Junction Based Routing (JBR), Extended Junction Based Routing (EJBR), Packet Switched Networks, On Chip Communication, Core Based Design
National Category
Embedded Systems
Identifiers
URN: urn:nbn:se:hj:diva-20128OAI: oai:DiVA.org:hj-20128DiVA: diva2:579826
Subject / course
JTH, Electrical Engineering
Presentation
2012-12-07, 13:00 (English)
Uppsok
Technology
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Examiners
Available from: 2013-01-17 Created: 2012-12-20 Last updated: 2013-01-17Bibliographically approved

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