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Low Power Capacitive Touch Digital Detection Filter: A Comparative Study of Synchronous and Asynchronous Methodologies
Norwegian University of Science and Technology, Faculty of Information Technology, Mathematics and Electrical Engineering, Department of Electronics and Telecommunications.
2012 (English)MasteroppgaveStudent thesis
Abstract [en]

In this thesis, both synchronous and asynchronous methodologies is explored for implementing a capacitive touch digital detection filter circuit. Asynchronous methodologies promise characteristics such as lower power, higher area cost and lower emission than synchronous methodologies. The aim of this thesis is to show if this can be exploited for this application. The synchronous implementation is written in Verilog, and follows a standard synchronous design flow. The asynchronous implementation is written in Balsa, and follows a Balsa Asynchronous Synthesis System design flow. Both implementations have been synthesised to netlist. A simple clock tree was generated for the synchronous implementation. Both netlists was simulated with wire load models. Netlist simulation of the synchronous and the asynchronous implementation shows that the power consumption is similar for the two implementations, because the fixed sample rate of the capacitance measurement operation dominates over the filter operations. The overhead from the handshake logic results in double the area for the asynchronous implementation. The asynchronous implementation has lower emission because of the randomness of the power consumption from the handshake circuits when the circuit is not sampling, while the synchronous implementation has large frequency components with harmonics from both clock flanks, resulting in higher emissions. Thus, asynchronous methodologies do not automatically lead to low power consumption, but can lead to larger area cost and lower emission. In addtion, new approaches for interfacing an asynchronous circuit, described in Balsa, with an analog circuit, and implementing a variable speed sampler clock with a minimum fixed sample period has been found, but not implemented.

Place, publisher, year, edition, pages
Institutt for elektronikk og telekommunikasjon , 2012. , 152 p.
Keyword [no]
ntnudaim:7392, MTEL elektronikk, Design av digitale systemer
URN: urn:nbn:no:ntnu:diva-19507Local ID: ntnudaim:7392OAI: diva2:570785
Available from: 2012-11-20 Created: 2012-11-20

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