Parameterizable Wishbone Bus
Independent thesis Basic level (university diploma), 10,5 credits / 16 HE creditsStudent thesis
In the industry of intellectual property products "IP-cores", a communication link is almost always needed. A semiconductor intellectual property IP core is a reusable unit of logic in electronic design. IP cores are used as building blocks for ASIC chip design or FPGA logic designs. A bus creates a communication link between the IP cores in a system.
The company AnaCatum Design AB have many projects where a bus is needed. Creating a new bus structure for every project is time consuming. By having a generic bus structure of a known standard with changeable parameters, the user only has to set the desired parameters to fit the system. Also having interfaces for master and slave the user has only to make minor changes to have a fully functional bus for the system.
Place, publisher, year, edition, pages
2012. , 93 p.
FPGA ASIC bus interconnection wishbone verilog
Other Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:liu:diva-85212ISRN: LITH-ISY-EX-ET--12/0399--SEOAI: oai:DiVA.org:liu-85212DiVA: diva2:566698
Subject / course
palmkvist, kent, Ph.D. Universitetslektor
Wikner, J Jacob, Ph.D. Universitetslektor