Current-Mode SAR-ADC In 180nm CMOS Technology
This thesis presents a fully differential 9-bit current-mode successive approximation (SAR) ADC. The circuit is designed in 0.18 um technology with 1.8 V supply voltage and has a current draw on 472 uA. The ADC has a sampling frequency on 50 MHz and has a maximum ENOB on 8.42 bit. Because of non-linearity will ENOB be input frequency dependent and degrade to 6.87 bit.
The design is based on conventional current-mode SAR ADC operation, but with a new comparator design and time interleaving. Time interleaving is used to increase the sampling frequency 10 times.
The circuit needs a high degree of matching to work properly. Sub-threshold operation in several current sources gives a high degree of uncertainty in the current value. Thus several calibration circuits are presented, but are not implemented.
Place, publisher, year, edition, pages
Institutt for elektronikk og telekommunikasjon , 2012. , 81 p.
ntnudaim:7642, MTEL elektronikk, Analog og blandet design
IdentifiersURN: urn:nbn:no:ntnu:diva-18820Local ID: ntnudaim:7642OAI: oai:DiVA.org:ntnu-18820DiVA: diva2:566295
Ytterdal, Trond, Professor