Modeling and Design of a Dual-Residue Pipelined ADC in 130nm CMOS
A 9-bit 50M S/s dual-residue pipelined ADC is modeled and analyzed. The
first stage is a modified pipelined ADC stage, while the other stages uses an
interpolator to resolve the signals, the focus is on designing these stages. The
dual-residue architecture is insensitive to the gain of the residue amplifiers, and
only a matching between two amplifiers is necessary. Limiting parameters of the
ADC is the offset in the residue amplifiers, as well as gain mismatch between
the amplifiers. The maximum allowed offset voltage of the residue amplifier is
Vlsb/2 , and maximum allowable mismatch between the two residue amplifiers is 1/256 for a 9-bit ADC. Multiple amplifier topologies were discussed and the best
candidate for residue amplification is found to be a zero-crossing based amplifier.
With this type of amplifier the last 8 stages of the ADC has an estimated power
consumption of 2.1mW.
Place, publisher, year, edition, pages
Institutt for elektronikk og telekommunikasjon , 2012. , 65 p.
ntnudaim:5790, MTEL elektronikk, Analog og blandet design
IdentifiersURN: urn:nbn:no:ntnu:diva-18558Local ID: ntnudaim:5790OAI: oai:DiVA.org:ntnu-18558DiVA: diva2:566075
Ytterdal, Trond, Professor