A Self-compensated, Bandwidth Tracking Semi-digital PLL Design in 65nm CMOS Technol-ogy
Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
In a conventional charge-pump based PLL design, the loop parameters such as the band-width, jitter performance, charge-pump current, pull-in range among others govern the ar-chitecture and implementation details of the PLL. Diﬀerent loop parameter speciﬁcationschange with a change in the reference frequency and inmost cases, requires careful re-designof some of the PLL blocks. This thesis describes the implementation of a semi-digital PLLfor high bandwidth applications, which is self-compensated, low-power and exhibits band-width tracking for all reference frequencies between 40 MHz and 1.6 GHz in 65nm CMOStechnology.This design can be used for a wide range of reference frequencies without redesigning anyblock. The bandwidth can be ﬁxed to some fraction of the reference frequency during designtime. In this thesis, the PLL is designed to make the bandwidth track 5% of the referencefrequency. Since this PLL is self-compensated, the PLL performance and the bandwidthremains same over PVT corners.
Place, publisher, year, edition, pages
2012. , 99 p.
PLL, semi-digital, Bandwidth tracking, Adaptive bandwidth, Compensation, PVT, Self-Bias, charge-pump, VCO, 65nm
Other Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:liu:diva-85143ISRN: LiTH-ISY-EX--12/4597--SEOAI: oai:DiVA.org:liu-85143DiVA: diva2:565415
Texas Instruments Deutschland GmbH
Subject / course
2012-08-21, Nollstället, 10:15 (English)
Wikner, J Jacob
Wikner, J Jacob