Test Scheduling with Power and Resource Constraints for IEEE P1687
Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
IEEE P1687 (IJTAG) is proposed to add more exibility|compared with IEEE 1149.1 JTAG|for accessing on-chip embedded test features called instruments. This exibility makes it possible to include and exclude instruments from the scan path. To reach a minimal test time, all instruments should be accessed concurrently. However, constraints such as power and resource constraints might limit concurrency. There is a need to consider power and resource constraints while developing the test schedule.
This thesis consists of two parts. In the rst part, three test time calculation approaches, namely session-based test schedule with a xed scan path, session-based test schedule with a recongurable scan path, and session-less test schedule with a recongurable scan path are proposed. In the second part, three test scheduling approaches, namely session-based test scheduling, optimized session-based test scheduling, and optimized session-less test scheduling are studied and three algorithms are presented for each of the test scheduling approaches. Experiments are carried out using the test scheduling approaches and the results show that optimized sessionless test scheduling can signicantly reduce the test time compared with session-based test scheduling.
Place, publisher, year, edition, pages
2012. , 44 p.
IJTAG, IEEE P1687, Test Time Calculation, Test Scheduling, Resource Constraints, Power Constraints
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:liu:diva-81472ISRN: LIU-IDA/LITH-EX-A--12/004--SEOAI: oai:DiVA.org:liu-81472DiVA: diva2:552757
Subject / course
Computer and information science at the Institute of Technology
Donald Knuth, Linköpings universitet, Linköping (English)