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Speeding up matrix computation kernels by sharing vector coprocessor among multiple cores on chip
Jönköping University, School of Engineering, JTH, Computer and Electrical Engineering.
2012 (English)Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
Abstract [en]

Today’s computer systems develop towards less energy consumption while keeping high performance. These are contradictory requirement and pose a great challenge. A good example of an application were this is used is the smartphone. The constraints are on long battery time while getting high performance required by future 2D/3D applications. A solution to this is heterogeneous systems that have components that are specialized in different tasks and can execute them fast with low energy consumption. These could be specialized i.e. encoding/decoding, encryption/decryption, image processing or communication.

At the apartment of Computer Architecture and Parallel Processing Laboratory (CAPPL) at New Jersey Institute of Technology (NJIT) a vector co-processor has been developed. The Vector co-processor has the unusual feature of being able to receive instructions from multiple hosts (scalar cores). In addition to this a test system with a couple of scalar processors using the vector processor has been developed. This thesis describes this processor and its test system. It also shows the development of math applications involving matrix operations. This results in the conclusions of the vector co-processing saving substantial amount of energy while speeding up the execution of the applications.

In addition to this the thesis will describe an extension of the vector co-processor design that makes it possible to monitor the throughput of instructions and data in the processor.

Place, publisher, year, edition, pages
2012.
Keyword [en]
Coprocessor, Speeding-up, Accelerator, Power efficiency, Shared resources, Vector processor, Multi-core on chip, Matrix algorithm, Matrix computation kernels
National Category
Embedded Systems
Identifiers
URN: urn:nbn:se:hj:diva-19292OAI: oai:DiVA.org:hj-19292DiVA: diva2:548182
External cooperation
New Jersey Institute of Technology
Subject / course
JTH, Computer and Electrical Engineering
Uppsok
Technology
Supervisors
Examiners
Available from: 2012-08-30 Created: 2012-08-29 Last updated: 2012-08-30Bibliographically approved

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CiteExportLink to record
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