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Very high aspect ratio through-silicon vias (TSVs) fabricated using automated magnetic assembly of nickel wires
KTH, School of Electrical Engineering (EES), Microsystem Technology.ORCID iD: 0000-0003-3452-6361
KTH, School of Electrical Engineering (EES), Microsystem Technology.ORCID iD: 0000-0002-4867-0391
KTH, School of Electrical Engineering (EES), Microsystem Technology.ORCID iD: 0000-0002-0441-6893
KTH, School of Electrical Engineering (EES), Microsystem Technology.
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2012 (English)In: Journal of Micromechanics and Microengineering, ISSN 0960-1317, E-ISSN 1361-6439, Vol. 22, no 10, 105001- p.Article in journal (Refereed) Published
Abstract [en]

Through-silicon via (TSV) technology enables 3D-integrated devices with higher performance and lower cost as compared to 2D-integrated systems. This is mainly due to smaller dimensions of the package and shorter internal signal lengths with lower capacitive, resistive and inductive parasitics. This paper presents a novel low-cost fabrication technique for metal-filled TSVs with very high aspect ratios (>20). Nickel wires are placed in via holes of a silicon wafer by an automated magnetic assembly process and are used as a conductive path of the TSV. This metal filling technique enables the reliable fabrication of through-wafer vias with very high aspect ratios and potentially eliminates characteristic cost drivers in the TSV production such as advanced metallization processes, wafer thinning and general issues associated with thin-wafer handling.

Place, publisher, year, edition, pages
Institute of Physics (IOP), 2012. Vol. 22, no 10, 105001- p.
Keyword [en]
Electronics packaging, Silicon wafers, Wire
National Category
Engineering and Technology
URN: urn:nbn:se:kth:diva-101062DOI: 10.1088/0960-1317/22/10/105001ISI: 000309219500001ScopusID: 2-s2.0-84866321637OAI: diva2:546126
EU, European Research Council, 277879

QC 20120827

Available from: 2012-08-27 Created: 2012-08-22 Last updated: 2012-12-07Bibliographically approved
In thesis
1. Integration and Fabrication Techniques for 3D Micro- and Nanodevices
Open this publication in new window or tab >>Integration and Fabrication Techniques for 3D Micro- and Nanodevices
2012 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

The development of micro and nano-electromechanical systems (MEMS and NEMS) with entirely new or improved functionalities is typically based on novel or improved designs, materials and fabrication methods. However, today’s micro- and nano-fabrication is restrained by manufacturing paradigms that have been established by the integrated circuit (IC) industry over the past few decades. The exclusive use of IC manufacturing technologies leads to limited material choices, limited design flexibility and consequently to sub-optimal MEMS and NEMS devices. The work presented in this thesis breaks new ground with a multitude of novel approaches for the integration of non-standard materials that enable the fabrication of 3D micro and nanoelectromechanical systems. The objective of this thesis is to highlight methods that make use of non-standard materials with superior characteristics or methods that use standard materials and fabrication techniques in a novel context. The overall goal is to propose suitable and cost-efficient fabrication and integration methods, which can easily be made available to the industry.

The first part of the thesis deals with the integration of bulk wire materials. A novel approach for the integration of at least partly ferromagnetic bulk wire materials has been implemented for the fabrication of high aspect ratio through silicon vias. Standard wire bonding technology, a very mature back-end technology, has been adapted for yet another through silicon via fabrication method and applications including liquid and vacuum packaging as well as microactuators based on shape memory alloy wires. As this thesis reveals, wire bonding, as a versatile and highly efficient technology, can be utilized for applications far beyond traditional interconnections in electronics packaging.

The second part presents two approaches for the 3D heterogeneous integration based on layer transfer. Highly efficient monocrystalline silicon/ germanium is integrated on wafer-level for the fabrication of uncooled thermal image sensors and monolayer-graphene is integrated on chip-level for the use in diaphragm-based pressure sensors.

The last part introduces a novel additive fabrication method for layer-bylayer printing of 3D silicon micro- and nano-structures. This method combines existing technologies, including focused ion beam implantation and chemical vapor deposition of silicon, in order to establish a high-resolution fabrication process that is related to popular 3D printing techniques.

Place, publisher, year, edition, pages
Stockholm: KTH Royal Institute of Technology, 2012. xv, 91 p.
TRITA-EE, ISSN 1653-5146 ; 2013:001
Microelectromechanical systems, MEMS, Nanoelectromechanical systems, NEMS, silicon, wafer-level, chip-level, through silicon via, TSV, packaging, 3D packaging, vacuum packaging, liquid encapsulation, integration, heterogeneous integration, wafer bonding, microactuators, shape memory alloy, SMA, wire bonding, magnetic assembly, self-assembly, 3D, 3D printing, focused ion beam, FIB
National Category
Engineering and Technology
urn:nbn:se:kth:diva-107125 (URN)978-91-7501-583-5 (ISBN)
Public defence
2013-01-18, F3, Lindstedtsvägen 26, KTH, Stockholm, 10:00 (English)

QC 20121207

Available from: 2012-12-07 Created: 2012-12-06 Last updated: 2016-08-11Bibliographically approved

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