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Design of a Low Power Cyclic/Algorithmic Analog-to-Digital Converter in a 130nm CMOS Process
Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
2012 (English)Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
Abstract [en]

Analog-to-digital converters are inevitable in the modern communication systems and there is always a need for the design of low-power converters. There are different A/D architectures to achieve medium resolution at medium speeds and among all those Cyclic/Algorithmic structure stands out due to its low hardware complexity and less die area costs. This thesis aims at discussing the ongoing trend in Cyclic/Algorithmic ADCs and their functionality. Some design techniques are studied on how to implement low power high resolution A/D converters. Also, non-ideal effects of SC implementation for Cyclic A/D converters are explored. Two kinds of Cyclic A/D architectures are compared. One is the conventional Cyclic ADC with RSD technique and the other is Cyclic ADC with Correlated Level Shift (CLS) technique. This ADC is a part of IMST Design + Systems International GmbH project work and was designed and simulated at IMST GmbH.

This thesis presents the design of a 12-bit, 1 Msps, Cyclic/Algorithmic Analog-to-Digital Converter (ADC) using the “Redundant Signed Digit (RSD)” algorithm or 1.5-bit/stage architecture with switched-capacitor (SC) implementation. The design was carried out in 130nm CMOS process with a 1.5 V power supply. This ADC dissipates a power of 1.6  mW when run at full speed and works for full-scale input dynamic range. The op-amp used in the Cyclic ADC is a two-stage folded cascode structure with Class A output stage. This op-amp in typical corner dissipates 631 uW power at 1.5 V power supply and achieves a gain of 77 dB with a phase margin of 64° and a GBW of 54 MHz at 2 pF load.

Place, publisher, year, edition, pages
2012. , 74 p.
Keyword [en]
Redundant Signed Digit, Correlated level Shifting, Low power, High Speed, Folded cascode
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
URN: urn:nbn:se:liu:diva-80132ISRN: LiTH-ISY-EX--12/4456--SEOAI: diva2:545838
External cooperation
IMST Design + Systems International GmbH
Subject / course
Electronics Systems
2012-06-11, Nollstället, Linköpings Universitet, Linköping, 14:30 (English)
Available from: 2012-08-29 Created: 2012-08-21 Last updated: 2012-08-29Bibliographically approved

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Puppala, Ajith kumar
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