Architecture Support and Comparison of Three Memory Consistency Models in NoC based Syst
2012 (English)In: Proceedings of 15th EUROMICRO Conference on Digital System Design: Architectures, Methods and Tools (DSD 2012), IEEE Computer Society, 2012, 304-311 p.Conference paper (Refereed)
We propose a novel hardware support for three relaxed memory models, Release Consistency (RC), Partial Store Ordering (PSO) and Total Store Ordering (TSO) in Network-on-Chip (NoC) based distributed shared memory multicore systems. The RC model is realized by using a Transaction Counter and an Address Stack based approach while the PSO and TSO models are realized by using a Write Transaction Counter and a Write Address Stack based approach. In the experiments, we use a configurable platform based on a 2D mesh NoC using deflection routing policy. The results show that under synthetic workloads, the average execution time for the RC, PSO and TSO models in 8x8 network (64 cores) is reduced by 35.8%, 22.7% and 16.5% respectively, over the Sequential Consistency (SC) model. The average speedup for the RC, PSO and TSO models in the 8x8 network under different application workloads is increased by 34.3%, 10.6% and 8.9%, respectively, over the SC model. The area cost for the TSO, PSO and RC models is increased by less than 2% over the SC model at the interface to the processor.
Place, publisher, year, edition, pages
IEEE Computer Society, 2012. 304-311 p.
Memory consistency; Release consistency; Scalability; Distributed shared memory; Network-on-Chip
Computer Systems Embedded Systems
IdentifiersURN: urn:nbn:se:kth:diva-95668DOI: 10.1109/DSD.2012.27ScopusID: 2-s2.0-84872916345ISBN: 978-076954798-5OAI: oai:DiVA.org:kth-95668DiVA: diva2:528985
15th EUROMICRO Conference on Digital System Design:Architectures, Methods and Tools (DSD 2012), September 5-8, 2012, Cesme, Izmir, Turkey
QC 201210162012-10-162012-05-282013-10-15Bibliographically approved