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Design and Implementation of a high-efficiency low-power analog-to-digital converter for high-speed transceivers
Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
2012 (English)Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
Abstract [en]

Modern communication systems require higher data rates which have increased thedemand for high speed transceivers. For a system to work efficiently, all blocks ofthat system should be fast. It can be seen that analog interfaces are the main bottleneckin whole system in terms of speed and power. This fact has led researchersto develop high speed analog to digital converters (ADCs) with low power consumption.Among all the ADCs, flash ADC is the best choice for faster data conversion becauseof its parallel structure. This thesis work describes the design of such a highspeed and low power flash ADC for analog front end (AFE) of a transceiver. Ahigh speed highly linear track and hold (TnH) circuit is needed in front of ADCwhich gives a stable signal at the input of ADC for accurate conversion. Twodifferent track and hold architectures are implemented, one is bootstrap TnH andother is switched source follower TnH. Simulations show that high speed with highlinearity can be achieved from bootstrap TnH circuit which is selected for the ADCdesign.Averaging technique is employed in the preamplifier array of ADC to reduce thestatic offsets of preamplifiers. The averaging technique can be made more efficientby using the smaller number of amplifiers. This can be done by using the interpolationtechnique which reduces the number of amplifiers at the input of ADC. Thereduced number of amplifiers is also advantageous for getting higher bandwidthsince the input capacitance at the first stage of preamplifier array is reduced.The flash ADC is designed and implemented in 150 nm CMOS technology for thesampling rate of 1.6 GSamples/sec. The bootstrap TnH consumes power of 27.95mW from a 1.8 V supply and achieves the signal to noise and distortion ratio(SNDR) of 37.38 dB for an input signal frequency of 195.3 MHz. The ADC withideal TnH and comparator consumes power of 78.2 mW and achieves 4.8 effectivenumber of bits (ENOB).

Place, publisher, year, edition, pages
2012. , 103 p.
Keyword [en]
Analog front end, data rates, Analog to digital converter, track and hold, bootstrap, averaging, interpolation
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
URN: urn:nbn:se:liu:diva-77178ISRN: LiTH-ISY-EX--11/4542--SEOAI: diva2:525399
Subject / course
Electronics Systems
2011-12-21, Nollstället, Linkoping, 15:15 (English)
Available from: 2012-05-15 Created: 2012-05-07 Last updated: 2012-05-15Bibliographically approved

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Younis, Choudhry Jabbar
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