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KTH, School of Information and Communication Technology (ICT).
2012 (English)Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
Abstract [en]

High speed data communication has brought a monumental change in both the modern human experience and in the pace of technological advancements. Processing and communication of data are closely associated with each other and are accomplished normally through broadly termed processor-based systems. Traditional buses have become a bottleneck in these systems with ever increasing demands in speed and bandwidth. This is due to their inability to scale in parallel with the increasing resources, speed requirements and complexities. Network-on-Chip has offered a sustainable solution to this problem and is aimed to replace the traditional buses.

This thesis presents multiple solutions to a multi-board Network-on-Chip Communication System for upgrading the data-rate several times through the links; and for eliminating a persistent breakdown of communication protocol. The thesis builds upon a 4x4 Network-on-Chip having 16 processor-nodes implemented on four interconnected plesiochronous Altera Stratix-II FPGA boards. Although the communication in on-chip network was fast and robust for obvious reasons, the Inter-board communication was incapable of high speed data transfer. It severely limited the performance of the whole Network-on-Chip and marred the advantages that it has over traditional bus-based systems.

The thesis utilizes several optimizations and techniques to enable an error-prone wired-link to successfully transfer signals and clock at high speed. It also introduces a fault tolerance technique for accuracy of data transfer through the network and also reduces the logic size of the communication mechanism. It involves multi-pronged approach for the challenges posed by deteriorating clock and signal integrity towards a successful and desirable communication. A test system is also developed to investigate the problems restricting the clock rate, and to test the accuracy of the data transfer. The test system, being balanced in distribution of data, is applied to the original design as well as to the new solutions proposed.

Place, publisher, year, edition, pages
2012. , 62 p.
Trita-ICT-EX, 52
National Category
Engineering and Technology
URN: urn:nbn:se:kth:diva-93801OAI: diva2:524013
Subject / course
Electronic- and Computer Systems
Educational program
Master of Science - System-on-Chip Design
Available from: 2012-04-27 Created: 2012-04-27 Last updated: 2012-04-27Bibliographically approved

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