Frame rate limiter for export restricted cameras
Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
This master thesis describes the design of a low power and low noise CMOS circuit capable of limiting 9 frames per second. This is a part of a larger ongoing project for development and design of a low-cost IR night-vision network camera. This circuit is implemented in 0.35μm process. An RC-oscillator with voltage averaging feedback concept is used as timing reference which is capable of overcoming ± 20% of frequency variations.
The circuit consumes 85 μW power when enabled and 1.853 μW power when disabled. This circuit design allows 9 frames per second. The variation in frequency due to a temperature range of -40°C to 100°C is within ±2.5% and for voltage range of 3.2V to 3.6V is within ±1%.
Place, publisher, year, edition, pages
2012. , 34 p.
Other Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:liu:diva-76716ISRN: LiTH-ISY-EX--12/4549--SEOAI: oai:DiVA.org:liu-76716DiVA: diva2:516336
Subject / course
2012-02-29, Systemet, Linköping Universitet, Linköping, 10:00 (English)