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FPGA Platform for Debug
KTH, School of Information and Communication Technology (ICT).
2012 (English)Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
Abstract [en]

FPGA-based prototyping is increasingly used in ASIC developments today to allow hardware/software co-design well ahead of chip fabrication and acceleration of functional verification of ASIC designs and the surrounding system. This thesis addresses an FPGA platform that can be applied in the development of next generation target debugger system. This FPGA platform can also be used for prototyping and verification acceleration of Ericsson ASIC IP:s.

Micro Ericsson ASIC (μ-EA) system is implemented in Xilinx Virtex-6 FPGA board with the SERDES port that can be tested at 1.25/2.5Gbps. This design costs 62% of FPGA device resources at a frequency of 2.5MHz. The access of Trace Buffer, MEMORY and DSP inside μ-EA proves achievable as well. Moreover, DSP core inside μ-EA is capable of running software and sending out trace messages to debug block, using DebugTool through a Nexus trace probe.

This FPGA platform combined with probe and debug tools developed by Ericsson Digital ASIC Unit can be used to verify and validate the next generation debugger systems before ASIC arrives.

Place, publisher, year, edition, pages
2012. , 84 p.
Trita-ICT-EX, 47
National Category
Engineering and Technology
URN: urn:nbn:se:kth:diva-92244OAI: diva2:512899
Subject / course
Electronic- and Computer Systems
Educational program
Master of Science - System-on-Chip Design
Available from: 2012-03-29 Created: 2012-03-29 Last updated: 2012-03-29Bibliographically approved

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