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Low Power UDP/IP Accelerator for IM3910 Processor
KTH, School of Information and Communication Technology (ICT).
2012 (English)Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
Abstract [en]

Due to their attractive flexibility and high productivity, general purpose processors (GPPs) are found to be spreading over large domain of applications. The growing complexity of modern applications results in high performance demands and as a response, several solutions have came to fulfill these demands. One of these solutions is to couple the GPP with a hardware accelerator to off-load critical functionalities.

In this thesis, A UDP/IP hardware accelerator is build to and coupled with an existing GPP with DMA interface, namely IM3910 form Imsys Technology AB in Stockholm, Sweden.

The main goal of this thesis is to investigate the semantics of coupling the accelerator with IM3910 and to characterize its area, performance and power consumption. Building this UDP/IP accelerator started from an initial version taken from "OpenCore" and then it was completed and optimized to suit the project needs. After verifying the accelerator at RTL, it was prototyped using Altera FPGA and connected to IM3910 through the DMA. In the last step, the accelerator was synthesized to gate-level netlist using 90nm technology library and characterized in-terms of area, performance and power consumption.

Place, publisher, year, edition, pages
2012. , 49 p.
Trita-ICT-EX, 42
National Category
Engineering and Technology
URN: urn:nbn:se:kth:diva-92241OAI: diva2:512890
Subject / course
Electronic- and Computer Systems
Educational program
Master of Science - System-on-Chip Design
Available from: 2012-03-29 Created: 2012-03-29 Last updated: 2012-03-29Bibliographically approved

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