Accurate Performance Exploration of System-on-Chip using TLM
Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
Increased complexity of system-on-chips (SoC) makes performance exploration with register transfer level (RTL) models to be both time consuming and to appear too late in the design cycle. Instead of RTL, transaction level models (TLM) have emerged as a dominant candidate for modeling of these complex SoCs. Transaction level models are abstracting implementation details and are therefore less complex to implement and execute much faster than RTL. However, an open issue is to define and measure how accurate TLM models are as compared to RTL. In this thesis, accuracy of a TLM model is defined and quantified by introducing metrics that are used to compare RTL and TLM models. The metrics introduced are transaction time, start time, relative throughput and transaction reordering. From the metrics, an error between RTL and TLM is calculated and presented.
The thesis discusses how to generate proper stimuli for models, collect the metric, and how to calculate and represent the error to the designer. The proposed methodology for accuracy measurement is using TLM2 definitions and may therefore be applied to any TLM model. This methodology is applied to experiment a multi-port memory that is modeled as an approximately timed TLM. Defined metrics are collected from the same scenarios applied to both RTL and TLM models. Accuracy measurements at system and sub-system level can be integrated with the verification environment to systematically develop and refine accurate TLM models for performance exploration
Place, publisher, year, edition, pages
2012. , 56 p.
Engineering and Technology
IdentifiersURN: urn:nbn:se:kth:diva-92231OAI: oai:DiVA.org:kth-92231DiVA: diva2:512839
Subject / course
Electronic- and Computer Systems
Master of Science - System-on-Chip Design
Hemani, Ahmed, Professor