Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE credits
A new quadrature receiver architecture is studied and designed in this thesis. In conventional quadrature receivers each of I and Q channels are downconverted separately using a mixer and a local oscillator (LO) in each path. On the other hand, the proposed architecture is based on multiplexed LO signals. As a result of multiplexing, just one LO buffer and one mixer are needed.
A top-down approach is used in the design of this receiver front-end. In the first design phase, a theoretical proof for the multiplexed LO down-conversion is provided. After that, the ideal and non-ideal system level design is performed using Agilent’s ADS. At system level, the bit error rate, sensitivity, and selectivity of the receiver are carried out using for example, a Gaussian MSK modulation/demodulation. The next phase is the circuit level design. The LNA, mixer, frequency divider, LO multiplexer-buffer, demultiplexer, and baseband amplifier circuits are designed in Cadence using a 65nm CMOS technology. Different simulation setups and analyses, such as DC, AC, transient, HB, S-parameters, PSS, PAC, and NF are used in designing the sub-circuits of the receiver. The last phase of the design consists of floorplaning and layout of the chip.
The completed receiver front-end circuit is simulated in transient mode for RF signals at 1GHz with data bandwidth of 1MHz. The receiver circuit consumes 38 mW power using a 1.2 V supply voltage.
2011. , 67 p.
Rusu, Ana, Univ. lektor